CS5535 datasheet(58/555 Pages) NSC

58 / 555 page

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Revision 0.8

Global Concepts and Features (Continued)

3.5.2

Clock Controls and Setup

Each of the clock domains listed in Table 3-3 is subject to

various GLCP controls and status registers except those

with “Note 3”. These registers and a brief description of

each is provided:

• GLCP Clock Active (GLCP_CLKACTIVE), MSR

51700011h: A 1 indicates the corresponding clock is

active. This is a read only register.

• GLCP Clock Control (GLCP_CLKOFF), MSR

51700010h: A 1 indicates the corresponding clock is to

be disabled immediately and unconditionally. Not

normally used operationally. Debug only.

• GLCP Clock Mask for Debug Clock Stop Action

(GLCP_CLKDISABLE), MSR 51700012h: A 1 indicates

the corresponding clock is to be disabled by debug logic

via a debug event or trigger. Not normally used opera-

tionally. Debug only.

• GLCP Clock Active Mask for Suspend Acknowledge

(GLCP_CLK4ACK), MSR 51700013h: A 1 indicates the

corresponding clock is to be monitored during a power

management Sleep operation. When all the clocks with

associated 1s go inactive, the GLCP sends a Sleep

Acknowledge to the Power Management Controller. This

the CLK_DLY_EN bit in GLCP_GLB_PM (MSR

5170000Bh[1]) to be 0.

• GLCP Clock Mask for Sleep Request

(GLCP_PMCLKDISABLE), MSR 51700009h: A 1 indi-

cates the corresponding clock is to be disabled uncondi-

tionally during a power management Sleep operation.

Clocks are disabled when the GLCP completes all of its

Sleep Request operations and sends a Sleep Acknowl-

edge to the Power Management Controller.

All of the registers above have the same layout, where

each bit is associated with a clock domain. The layout and

recommended operating values for the registers is pro-

vided in Table 5-73 "Clock Mapping / Operational Settings"

on page 518.

3.5.2.1

Additional Setup Operations

• GLCP Debug Clock Control (GLCP_DBGCLKCTL),

MSR 51700016h: Set all bits to 0. This turns off all

clocks to debug features; not needed during normal

operation.

• GLCP Global Power Management Control

(GLCP_GLB_PM), MSR 5170000Bh: Set all bits to 0.

This disables the use of the fixed delay in

GLCP_CLK_DIS_DELAY and enables the use of

GLCP_CLK4ACK.

• GLCP Clock Disable Delay Value

(GLCP_CLK_DIS_DELAY), MSR 51700008h: Set all

bits to 0. Since use of this register is disabled by setting

all GLCP_DBGCLKCTL bits to 0, the actual value of this

If use of GLCP_CLK_DIS_DELAY is desired, set the

CLK_DLY_EN bit in GLCP_GLB_PM (MSR

5170000Bh[1] = 1). This will disable the use of

GLCP_CLK4ACK and shut off the clocks in

GLCP_PMCLKDISABLE after the

GLCP_CLK_DIS_DELAY expires. This delay is

measured in PCI clock edges.

3.6

RESET CONSIDERATIONS

The elements that effect “reset” within the CS5535 are

illustrated in Figure 3-6 on page 59. The following points

are significant:

• Signals denoted in upper case (i.e., all capitals) are

external pins. Signals denoted in lower case are internal

signals.

• There are separate resets for the Working power domain

(RESET_WORK#) and the Standby power domain

(RESET_STAND#).

• All elements in the figure are within the Standby power

domain and operate off the KHZ32_CLK.

• The TAP Controller is in the Working power domain, but

it may be reset separately from the other Working

domain logic.

• Any time the CS5535 is in the Standby state, the

Working power domain is unconditionally and immedi-

ately driven into reset.

• Any faulted event or external reset input forces the

CS5535 into the Standby state.

• External reset (RESET_OUT#) is always asserted

immediately with internal working domain reset but is

de-asserted subject to a programmable delay.

RESET_OUT# asserts without any clocks but requires

the KHZ32_CLK for the delay and the PCI_CLK to de-

assert.

• IDE_RESET# is always asserted immediately with

internal working domain reset and de-asserts when the

ATAC comes out of reset, that is, within a few

MHZ66_CLK edges of internal reset de-assert.

• LVD monitors VCORE and only asserts

power_good_working when VCORE is within normal

operating range.

• LVD monitors VCORE_VSB and VIO_VSB along with

RESET_STAND#. The assertion of power_good_standy

only occurs when the voltages are within normal oper-

ating range and RESET_STAND# is high, that is, de-

asserted.

When power is applied to the CS5535 from a completely

cold start, that is, no Standby or Working power, both

RESET_STAND# and RESET_WORK# are applied. Alter-

natively, one or both of the reset inputs may be tied to

Standby I/O power (VIO_VSB), and the LVD circuit will gen-

erate internal Power Good Working and internal Power

Good Standby. Assuming the LVD circuit is enabled

(LVD_EN# pin tied low), Power Good Standby will assert

until proper Standby voltages have been achieved and

RESET_STAND# has been de-asserted.

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