CS5535 datasheet(256/555 Pages) NSC

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Revision 0.8

ATAC Register Descriptions (Continued)

5.4.2.4

Channel 0 Drive 0 DMA (ATAC_CH0D0_DMA)

If MSR 50302021h[31] = 1, Format 1. Allows independent control of command and data.

Format 1 settings for:

PIO Mode 0 = F7F4F7F4h

PIO Mode 1 = 53F3F173h

PIO Mode 2 = 13F18141h

PIO Mode 3 = 51315131h

PIO Mode 4 = 11311131h

31:28

t2IC

Command Cycle Recovery Time. Value + 1 cycle.

27:24

t3C

Command Cycle IDE_IOW# Data Setup. Value + 1 cycle.

23:20

t2WC

Command Cycle IDE_IOW# Pulse Width Minus t3. Value + 1 cycle.

19:16

t1C

Command Cycle Address Setup Time. Value + 1 cycle.

15:12

t2ID

Data Cycle Recovery Time. Value + 1 cycle.

11:8

t3D

Data Cycle IDE_IOW# Data Setup. Value + 1 cycle.

7:4

t2WD

Data Cycle IDE_IOW# Pulse Width Minus t3. Value + 1 cycle.

3:0

t1D

Data Cycle Address Setup Time. Value + 1 cycle.

Note:

in 66 MHz clock cycles. The ‘value’ that is entered is the desired number of 66 MHz clock cycles in hexadecimal;

the actual parameter timing generated by that entry is the entered ‘value’ plus the indicated number of ‘cycles’

(‘n’) as listed in the description of that parameter.

MSR Address

51300021h

Type

R/W

Reset Value

00000000_00077771h

ATAC_CH0D0_DMA Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

MODE66_SEL

RSVD

tKR

tDR

tKW

tDW

MODE66_SEL

RSVD

tCRC

tSS

tCYC

tRP

tACK

ATAC_CH0D0_PIO Bit Descriptions (Continued)

Bit

Name

Description

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