CS5535 datasheet(258/555 Pages) NSC

258 / 555 page

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258

Revision 0.8

ATAC Register Descriptions (Continued)

5.4.2.5

Channel 0 Drive 1 PIO (ATAC_CH0D1_PIO)

Refer to Section 5.4.2.3 "Channel 0 Drive 0 PIO (ATAC_CH0D0_PIO)" on page 255 for bit descriptions.

5.4.2.6

Channel 0 Drive 1 DMA (ATAC_CH0D1_DMA)

Refer to Section 5.4.2.4 "Channel 0 Drive 0 DMA (ATAC_CH0D0_DMA)" on page 256 for bit descriptions.

5.4.2.7

PCI Abort Error (ATAC_PCI_ABRTERR)

5.4.3

ATAC Native Registers

5.4.3.1

Bus Master 0 Command - Primary (ATAC_BM0_CMD_PRIM)

MSR Address

51300022h

Type

R/W

Reset Value

00000000_00009172h

MSR Address

51300023h

Type

R/W

Reset Value

00000000_00077771h

MSR Address

51300024h

Type

R/W

Reset Value

00000000_00000000h

ATAC_PCI_ABRTERR Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Read: RSVD; Write: PCI_ABORT

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Read: RSVD; Write: PCI_ABORT

ATAC_PCI_ABRTERR Bit Descriptions

Bit

Name

Description

63:0

RSVD/PCI_ABORT

Reserved. Return 0 on read.

PCI Abort. Write (of any value) to this register will set bit 1 of Bus Master 0 Status

ATAC I/O Address 00h

Type

R/W

Reset Value

00h

ATAC_BM0_CMD_PRIM Register Map

RSVD

RWCTL

RSVD

BMCTL

ATAC_BM0_CMD_PRIM Bit Descriptions

Bit

Name

Description

7:4

RSVD

Reserved. Set to 0. Return 0 on read.

3RWCTL

Read or Write Control. Sets the direction of bus master transfers.

0: PCI reads performed.

1: PCI writes performed.

This bit should not be changed when the bus master is active.

2:1

RSVD

Reserved. Set to 0. Return 0 on read.

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