CS5535 datasheet(253/555 Pages) NSC

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ATAC Register Descriptions (Continued)

5.4.1.6

GeodeLink Device Diagnostic MSR (ATAC_GLD_MSR_DIAG)

This register is reserved for internal use by National and should not be written to.

49:48

IOMODEA

I/O Mode A Control. These bits determine how the associated IDE inputs and outputs

behave when the PMC asserts two internal signals that are controlled by PMS I/O Off-

set 20h and 0Ch. The list of affected signals is in Table 3-12 "Sleep Driven IDE Signals"

on page 72.

00: No gating of I/O cells during a Sleep sequence (Default).

01: During a power management Sleep sequence, force inputs to their non-asserted

state when PM_IN_SLPCTL is enabled.

10: During a power management Sleep sequence, force inputs to their non-asserted

state when PM_IN_SLPCTL is enabled, and park (force) outputs low when

PM_OUT_SLPCTL is enabled.

11: Immediately and unconditionally, force inputs to their not asserted state, and park

(force) outputs low.

47:4

RSVD

Reserved. Returns 0 on read.

3:2

PMODE1

Power Mode 1. Power mode for Channel 1 clock domain.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s cir-

cuits are not busy.

10: Reserved.

11: Reserved.

1:0

PMODE0

Power Mode 0. Power mode for Channel 0 clock domain.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s cir-

cuits are not busy.

10: Reserved.

11: Reserved.

MSR Address

51300005h

Type

R/W

Reset Value

00000000_00000000h

ATAC_GLD_MSR_PM Bit Descriptions (Continued)

Bit

Name

Description

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