CS5535 datasheet(100/555 Pages) NSC

100 / 555 page

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100

Revision 0.8

4.7

PROGRAMMABLE INTERVAL TIMER

The Programmable Interval Timer (PIT) generates pro-

grammable time intervals from the divided clock of an

external clock signal of a crystal oscillator. The PIT (8254)

has six modes of operation. Figure 4-14 shows the block

diagram of the PIT and its connectivity to the Local bus.

The 8254 is comprised of three independently programma-

ble counters. Each counter is 16 bits wide. A 14.318 MHz

external clock signal (from a crystal oscillator or an external

clock chip) is divided by 12 to generate 1.19 MHz, which is

used as a clocking reference for these three counters.

Each counter is enabled or triggered with its GATE signal.

Based on the counting mode, the counter concerned is

activated by a high level or a low-to-high transition of its

GATE signal.

Each counter has its output signal, whose shape is depen-

dent upon the counter’s operational mode. The Control reg-

ister loads the counters and controls the various modes of

operation. This Control register controls the operation

mode of the control logic (counter state machine), which in

turn controls the counter, the high-order and low-order out-

put latches. A status latch is also present in the 8254 and is

used to output status information.

Features include:

• Comprised of three 16-bit wide counters.

• Supports read-back and counter latch commands.

• Supports six modes of counting.

• Allows several counter latch commands in parallel with

the read-back command.

Figure 4-14. PIT Block Diagram

CPU

Local Bus

PIT Shadow

Divide By 12

Timer 0

Timer 1

Timer 2

GeodeLink Adapter

Control

14 MHz

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