CS5535 datasheet(86/555 Pages) NSC

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ACC Functional Description (Continued)

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Slot 12: GPIO Status

This slot returns the pin status of the AC97 codec’s GPIO

pins (if implemented).

bits [19:4]

Value of the GPIO pins

(Up to 16 can be implemented)

bits [3:1]

Reserved

bit 0

GPIO_INT input pin event interrupt

(1 = Event; 0 = No Event)

Bit[0] indicates that there was a transition on one of the

unmasked codec GPIO pins (see AC97 Codec Specifica-

tion v2.1 for details). If the Codec GPIO Interrupt Enable bit

is set, then slot 12, bit[0] = 1 will trigger an IRQ and set the

Codec GPIO Interrupt Flag bit.

4.3.5

AC Link Power Management

4.3.5.1

AC Link Power-down

The AC Link interface signals can be placed in a low power

mode by programming the AC97 codec’s Power-down Con-

trol/Status register. When this is performed, both the

AC_CLK and AC_S_IN are brought to a low voltage level

by the AC97 codec. This happens immediately following

the write to the AC97 codec’s Power-down Control/Status

frame signaling power-down. After powering down the AC

Link, the ACC must keep AC_S_SYNC and AC_S_OUT

low; hence, all the AC Link signals (input and output) are

driven low.

AC_CLK is de-asserted at the same time that bit[4] of slot 2

is being transmitted on the AC Link. This is necessary

because the precise time when the codec stops AC_CLK is

not known.

4.3.5.2

AC Link Wakeup (Warm Reset)

A warm reset re-activates the AC Link without altering the

registers in the AC97 codec. The ACC signals the warm

reset by driving AC_S_SYNC high for a minimum of 1 µs in

the absence of the AC_CLK. This must not occur for a min-

imum of four audio frame periods following power-down

(note that no bit clock is available during this time).

AC_S_SYNC is normally a synchronous signal to AC_CLK,

but when the AC97 codec is powered down, it is treated as

an asynchronous wakeup signal. During wakeup, the AC97

codec does not re-activate the bit clock until AC_S_SYNC

is driven high (for 1 µs minimum) and then low again by the

ACC. Once AC_S_SYNC is driven low, AC_CLK is re-

asserted.

See "Audio Driver Power-up/down Programming Model" on

page 90 for additional power management information and

programming details.

4.3.6

Bus Mastering Buffer Scheme

Because the bus masters must feed data to the codec with-

out interruption, they require a certain amount of data buff-

ering.

The 32-bit bus masters (stereo) use 24 bytes of buffer

space, and the 16-bit bus masters (mono) use 20 bytes of

buffer space. A bus master will always do buffer fill/empty

requests whenever it can transfer 16 bytes of data. It will

attempt to do transfers of 16 bytes on a 16-byte boundary,

whenever possible. A bus master may do a transfer of more

(if it is just starting, and sufficient buffer space is available)

or less than 16 bytes (to bring itself onto a 16-byte bound-

ary). It may also do a transfer of less than 16 bytes if the

size of the physical memory region causes it to end on a

non-16 byte boundary.

Some important details on how a bus master behaves:

• When an outgoing bus master is enabled, it begins

sending data over the AC Link as soon as data is avail-

able in its buffer. The slot valid tag for its slot will be

asserted beginning with the first audio sample.

• When a bus master is disabled while operating, any data

in its buffer is lost. Re-enabling the bus master begins

by fetching a PRD.

• If the bus master is paused during recording or play-

back, the data in its buffer remains there in a frozen

state. Once resumed, it continues as if nothing has

occurred. If the bus master is playing back data, the

output slots corresponding to the bus master are tagged

invalid while it is in the paused state.

• If a buffer underrun occurs on an outgoing bus master,

the output slots corresponding to the bus master are

tagged invalid until data becomes available.

• If a buffer overrun occurs on an incoming bus master,

samples coming in on the serial link are tossed away

until space becomes available in the bus master’s buffer.

4.3.7

ACC Software Programming

4.3.7.1

Physical Region Descriptor (PRD) Table

Address Register

Before a bus master starts a transfer it must be pro-

grammed with a pointer to a Physical Region Descriptor

(PRD) table. This is done by writing to the bus master’s

PRD Table Address register. This pointer sets the starting

memory location of the PRD table. The PRDs in the PRD

table describe the areas of memory that are used in the

data transfer. The table must be aligned on a 4-byte bound-

ary (DWORD aligned).

4.3.7.2

Physical Region Descriptor Format

Each physical memory region to be transferred is

described by a PRD as illustrated in Table 4-6 on page 87.

The PRD table must be created in memory by software

before the bus master can be activated. When the bus

master is enabled by setting its Bus Master Enable bit, data

transfer begins, with the PRD table serving as the bus mas-

ter’s “guide” for what to do. The bus master does not cache

PRDs.

A PRD entry in the PRD table consists of two DWORDs.

The first DWORD contains a 32-bit pointer to a buffer to be

transferred (Memory Region Base Address). The second

DWORD contains control flags and a 16-bit buffer size

value. The maximum amount of audio data that can be

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