Preliminary Technical Data

AD5100

Rev. PrJ | Page 25 of 32

111 – Never Occur

[7] – Reserved

Notes

1.

Values AD5100 has when shipped from manufacturer’s factory.

2.

3.

lots of activity. Setting these bits is an added means of ensuring any erroneous activity on the bus does not cause AD5100 special functions to

become active.

I2C Serial Interface

serial bus. The AD5100 is connected to this bus as a slave device

(the AD5100 has no master capabilities).

The AD5100 has a 7-bit slave address. The six MSBs are 010111

and the LSB is determined by the state of the A0 pin. Therefore

when A0 is low, the AD5100 slave address is 01011110 and

0101111 otherwise. Therefore the A0 pin allows the user to

devices comply with the configurations shown in Figure 20.

The 2-wire serial bus protocol operates as follows:

1.

The master initiates data transfer by establishing a

START condition, which is when SDA goes from

high-to-low while SCL is high. The following byte is

the slave address byte, which consists of the 7-bit slave

address followed by an R/W bit which determines

whether data is read from or written to the slave

device

2.

Data is transmitted over the serial bus in sequences of

nine clock pulses (eight data bits followed by an

Acknowledge bit). The transitions on the SDA line

must occur during the low period of SCL and remain

stable during the high period of SCL.

3.

When all data bits have been read or written, a STOP

condition is established by the master. A STOP

condition is defined as a low-to-high transition on the

SDA line while SCL is high. In write mode, the master

establish a STOP condition. In the read mode, the

(i.e., the SDA line remains high). The master then

STOP condition.

For the AD5100, write operations contain either one or two

bytes, while read operations contain one byte. The AD5100

makes use of an Address Pointer Register. The Address Pointer

Register does not have and does not require an address, because

it is the register to which the first data byte of every write

operation is written automatically. This data byte is an address

pointer that sets up one of the other registers for the second

byte of the write operation or for a subsequent read operation.

Table 10 shows the structure of the Address Pointer Register.

Bits [6:0] signify the address of the register that is to be written

to or read from. Bit [7] is used when OTP mode is invoked (use

of this bit is explained later in the OTP section), and should be

‘0’ for normal write/read operations.

Table 10

– Address Pointer Register Structure

Bit #

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Function

OTP En

AP6

AP5

AP4

AP3

AP2

AP1

AP0

Writing Data to AD5100

When writing data to the AD5100, the user begins by writing

an address byte followed by the R/W bit set to ‘0’. The AD5100

will acknowledge (if the correct address byte is used) by pulling

follows with two data bytes. The first data byte is the address of

the internal data register to be written to, which is stored in the

Address Pointer Register. The second byte is the data to be

written to the internal data register. After each byte the AD5100

pulse. Figure 21 illustrated this operation.

SDA

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

ADDRESS POINTER BYTE

FRAME 3

DATA BYTE

SCL

ACK. BY

AD5100

ACK. BY

AD5100

ACK. BY

AD5100

STOP BY

MASTER

START BY

MASTER

0

1

0

1

1

AD0 R/W

OTP AP6 AP5 AP4 AP3 AP2 AP1 AP0

D7

D4

D3

D2

D1

D0

03437-0-035

1

D6

D5