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AD5100EVAL датащи(PDF) 23 Page - Analog Devices |
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AD5100EVAL датащи(HTML) 23 Page - Analog Devices |
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23 / 32 page ![]() Preliminary Technical Data AD5100 Rev. PrJ | Page 23 of 32 B W [2:0] – 3 bits used to program RESET Hold time [7:3] – Reserved (200 mS) 0x0 C R/W Y Watchdog Timeout [2:0] – 3 bits used to program Watchdog timeout time [7:3] – Reserved 0x00 (1500 mS) 0x0 D R/ W Y RESET Configuration [0] – 0 - RESET is active when SHDN is active 1 - RESET is not active when SHDN is active [1] – Reserved [2] – 0 - Enable V4MON over threshold to cause RESET 1 - Prevent V4MON over threshold to cause RESET (For V4OUT Application) [3] – 0 - Prevent floating WDI to cause RESET 1 - Enable floating WDI to cause RESET [7:4] – Reserved 0x00 0x0E R/ W Y SHDN Rail Voltage Configuration [2:0] – Reserved [3] – 0 - SHDN rail = V1MON 1 - SHDN rail = Vreg [7:4] – Reserved 0x00 0x0F R/ W Y Watchdog Mode [2:0] – Reserved [3] – 0 – Standard Mode 1 – Advanced Mode [7:4] – Reserved 0x00 0x15 R/ W Y Program Lock Fuse (Inhibit Further Programming) [2:0] – Reserved [3] – 0 – Fuse Programming allowed 1 – Fuse Programming Disabled [7:4] – Reserved 0x00 0x16 R/ W N Special Functions 1 [0] – 0 – OTP Enable A Inactive 1 – OTP Enable A Active [1] – 0 - OTP Enable B Inactive 1 - OTP Enable B Active [2] – 0 – Software assertion of SHDN Inactive 0x00 |
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