AD5100EVAL datasheet(17/32 Pages) AD

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Preliminary Technical Data

AD5100

Rev. PrJ | Page 17 of 32

Outputs

Shutdown Generator

The shutdown output, SHDN , is triggered by the abnormal

inputs of V1MON or V2MON. It can also be the result of a failed

watchdog input. SHDN control can also be asserted low by

users through I2C programming at anytime.

To be explicit, the shutdown generator asserts a logic-low

SHDN

signal based on the following conditions:

During power-up.

When V1MON goes over or under the threshold,

Figure 5.

When V2MON is below the turn-on threshold during

the rising edge or the turn-off threshold during the

falling edge in the default level sensitive mode,

Figure 5.

When the external monitoring processor cannot

issue the necessary WDI signal and an Advanced

WDI mode is selected, Figures 8 and 9.

I2C programmed-shutdown.

The SHDN signal is released after the programmable hold

time. The SHDN output is push-pull configured with I

selectable rail voltage of either V1MON in default or internal

VREG. Figure 15 shows the SHDN output configurations, Pull-

down resistor R1 ensures SHDN is pulled to ground when

the AD5100 is not powered. When AD5100 is powered, M2a

and M2b are both on. M2a has relatively lower impedance

than M2b and R1 that the SHDN remains low at shutdown.

When the AD5100 settles, sw1 will be on. M1 is stronger

than M2a that SHDN will be pulled to the rail that makes

AD5100 out of the shutdown mode.

The AD5100 is likely be used to monitor and control power

regulators in some applications where some regulators have

the input and enable pins next to each other in fine pitch that

may pose reliability concern under some abnormal

conditions. To prevent this may happen, the AD5100

shutdown output features a smart-load detection that ensures

the shutdown to respond for maximum protection. For

example, if the car battery has not been started for an

extensive period of time and a resistive dendrite may have

formed across the SHDN and the battery terminal (V1MON),

the dendrite will be blown immediately as the M2a is

designed with adequate current sinking capability and

remains in the on position to offer such protection. In

another situation where the SHDN pin may be hard-shorted

to any sub-30V source, the short-circuit detector will open

sw2 and therefore limit the current by the high impedance

M2b.

Figure 15. Shutdown Output. # = I2C Selectable, * = Default.

Reset Generator

The Reset output, RESET , is triggered by the abnormal input

of V3MON or V4MON. RESET activation can also be the result of

the processor that is not generating the proper watchdog

signal or the Manual Reset is triggered.

To be explicit, the Reset generator asserts a logic-low RESET

signal based on the following conditions

During power up

When V3MON drops below the threshold, Figure 8.

When V4MON drops below the threshold, Figure 10.

When SHDN output is asserted, Figures 5 and 13.

When the external monitoring processor cannot

issue the necessary WDI signal, Figures 12 and 13.

When MR is asserted, Figure 14.

The RESET signal is asserted and maintained except when it

is triggered by the WDI that will be described in the

watchdog section. The RESET signal is released after the

programmable hold time.

As shown in Figure 16, The RESET output is push-pull

configured with the the rail voltage of V3MON.

Figure 16. Reset Output.

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