TSI721 datasheet(25/67 Pages) RENESAS

номер детали	TSI721

подробное описание детали	Table of Contents

PDF	67 Pages

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25 / 67 page

Tsi721 Datasheet

April 4, 2016

Integrated Device Technology

SP_SWAP_TX

S-RIO transmit lane swap. This signal sets the reset value of the SWAP_TX bit

of RapidIO PLM Port Implementation Specific Control Register.

0 = Disable S-RIO port transmit lane swap.

1 = Enable S-RIO port transmit lane swap.

This signal is multiplexed with GPIO[8]. It is a static signal.

SR_BOOT

I-PD

Boot from S-RIO. It can be asserted high only when I2C_DISABLE is also high.

1 = The Tsi721 S-RIO link can start training immediately after a fundamental

reset and Tsi721 automatically sets the SRBOOT_CMPL bit of Device Control

0 = The Tsi721 S-RIO link can start training only after software sets the

SRBOOT_CMPL bit.

It is a static signal.

STRAP_RATE[2:0]

I-PU

S-RIO link rate. These signals control the reset value of the BAUD_SEL field of

the RapidIO Port Control 2 CSR . Note that the BAUD_SEL encoding is different

than that of STRAP_RATE.

• 0b111 = 5 Gbaud

• 0b110 = 2.5 Gbaud

• 0b101 = 1.25 Gbaud

• 0b010 = 3.125 Gbaud

• Others: Reserved

It is a static signal.

Table 9: Power-Up Signals (Continued)

Name

Pin Type

Description

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