TSI721 datasheet(22/67 Pages) RENESAS

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Tsi721 Datasheet

April 4, 2016

Integrated Device Technology

2.9

GPIO Signals

Table 7: GPIO Signals

Name

Pin Type

Description

GPIO[15:0]

Asynchronous general purpose I/O.

• Each GPIO pin can be configured as a general purpose I/O pin.

• Each pin can be configured as either an input or an output

• When configured as an output, GPIO[0] is asserted high when

BDMA/SMSG/PC2SR/SR2PC has an uncorrectable ECC error or S-RIO MAC

has a non-data memory uncorrectable ECC error

• When configured as an output, GPIO[1] is asserted high when Tsi721 PCIe

port is not in the data link active state

• When configured as an output, GPIO[2] is asserted high when Tsi721 has an

active interrupt (for more information, see Figure 18 and Figure 19)

• When configured as an output, GPIO[15:3] can be programmed through

software

GPIO[12:0] are used as power-up pins as displayed in Table 8. These signals

must remain stable for 4000 REFCLKP/REFCLKN cycles after RSTn is

de-asserted. They are ignored after reset.

Table 8: GPIO Mapping to Power-up Signals

GPIO Pin Name

(Primary Function)

Power-up Pin Namea

(Secondary Function)

a. For more information about these signals, see Power-up Signals.

GPIO[3:0]

I2C_SA[3:0]

GPIO[4]

I2C_DISABLE

GPIO[5]

I2C_SEL

GPIO[6]

I2C_MA

GPIO[7]

SP_SWAP_RX

GPIO[8]

SP_SWAP_TX

GPIO[9]

SP_HOST

GPIO[10]

SP_DEVID

GPIO[12:11]

CLKSEL[1:0]

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