TSI721 datasheet(59/67 Pages) RENESAS

номер детали	TSI721

подробное описание детали	Table of Contents

PDF	67 Pages

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Tsi721 Datasheet

April 4, 2016

Integrated Device Technology

Figure 15: LVPECL to REFCLKP/N / PCCLKP/N

3.7.6

JTAG and Test Interface Signal Timings

The following table lists the AC specifications for Tsi721’s JTAG and test interface.

Table 33: JTAG and Test Interface AC Specifications

Symbol

Parameter

Minimum Maximum

Units

Notes

TBSF

TCK frequency

MHz

TBSCH

TCK high time

Measured at 1.5V

TBSCL

TCK low time

Measured at 1.5V

TBSCR

TCK rise time

0.8V to 2.0V

TBSCF

TCK fall time

2.0V to 0.8V

TBSIS1

Input setup to TCK

TBSIH1

Input hold from TCK

TBSOV1

TDO output valid delay from falling edge of

TCK.a

a. Outputs precharged to VDD.

-15

TOF1

TDO output float delay from falling edge of

TCK

-15

TBSTRST1

TRSTn release before RSTn release

TRSTn must

become asserted

while RSTn is

asserted during

device power-up

TBSTRST2

TRSTn release before TMS or TDI activity

PCCLK/REFCLK

LVPECL

150

ohms

150

ohms

Clock source

ohms

3.3V

124

ohms

124

ohms

0.1uf

Tsi7xx

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