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TSI721 датащи(PDF) 60 Page - Renesas Technology Corp |
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TSI721 датащи(HTML) 60 Page - Renesas Technology Corp |
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60 / 67 page ![]() Tsi721 Datasheet 60 April 4, 2016 Integrated Device Technology 3.7.7 I2C Interface Signal Timings The following table lists the AC specifications for the I2C Interface of the Tsi721. 1. Not tested. 2. See timing diagram displayed in Figure 16. 3. After this period, the first clock pulse is generated. Figure 16: I2C Interface Signal Timings Table 34: I2C Interface AC Specifications Symbol Parameter Minimum Maximum Units Notes FSCL I2C_SCLK clock frequency 0 100 kHz - TLOW I2C_SCLK clock low time 4.7 - us See Notes 1 and 2. THIGH I2C_SCLK clock high time 4.0 - us See Notes 1 and 2. THDDAT Data hold time 0 3.45 us See Note 2. TSUDAT Data setup time 250 - ns See Note 2. TSR Rise time of I2C_SCLK and I2C_SD - 1000 ns See Note 2. TSF Fall time of I2C_SCLK and I2C_SD - 300 ns See Note 2. TBUF Bus free time between STOP and START condition 4.7 - us See Note 2. THDSTA Hold Time (repeated) START condition 4.0 - us See Notes 2 and 3. TSUSTA Setup time for repeated START condition 4.7 - us See Note 2. TSUSTO Setup time for STOP condition 4.0 - us See Note 2. SDA SCL TBUF Stop Start TLOW THDSTA THIGH TSR THDDAT TSF TSUDAT TSUSTA Repeated THDSTA TSP Stop TSUSTO Start |
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