AM79C901AVCT datasheet(63/90 Pages) AMD

63 / 90 page

Am79C901A

PR ELI M IN AR Y

TBR16: 10BASE-T Status and Enable Register (Register 16)

The status bits indicate when there is a change in the

Link Status, Duplex Mode, Auto-Negotiation status,

or Speed status. Register 16 contains the status and

enable bits. The status is always updated whether or

not the enable bits are set. When a status change oc-

curs, the system will need to read this register to

clear the status bits. See Table 50.

Table 50.

TBR16: 10BASE-T Status and Enable Register (Register 16)

Note:

All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.

Bits

Name

Description

Read/

Write

Default Value

(hex)

15:14

Reserved

Status Test Enable

(Note 1)

1 = When this bit is set, setting bits 12:9 of this register

will cause a condition that will set bits 4:1

accordingly. The effect is to test the register bits with

a forced interrupt condition.

0 = Bits 4:1 are only set if the interrupt condition (if any

bits in 12:9 are set) occurs.

R/W

Link Status Change

Enable

1 = Link Status change enable

0 = This interrupt is masked

R/W

Duplex Mode Change

Enable

1 = Duplex Mode change enable

0 = This interrupt is masked

R/W

Auto-Negotiation Change

Enable

1 = Auto-Negotiation change enable

0 = This interrupt is masked

R/W

Speed Change Enable

1 = Speed change enable

0 = This interrupt is masked

R/W

Global Enable

1= Global interrupt enable

0 = This interrupt is masked

R/W

7:5

Reserved

Link Status Change

1 = Link Status has changed on a port

0 = No change in Link Status

R, LH

Duplex Mode Change

1 = Duplex Mode has changed on a port

0 = No change in Duplex mode

R, LH

Auto-Negotiation Change

1 = Auto-Negotiation status has changed on a port

0 = No change in Auto-Negotiation status

R, LH

Speed Change

1 = Speed status has changed on a port

0 = No change

R, LH

Global

1 = Indicates a change in status of any of the above

interrupts

0 = Indicates no change in Interrupt status

R, LH

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