AM79C901AVCT datasheet(22/90 Pages) AMD

22 / 90 page

Am79C901A

PR ELI M IN AR Y

BASIC FUNCTIONS

Network Interfaces

The Am79C901A PHY contains an integrated 1 Mbps

home networking PHY and a 10BASE-T PHY. This de-

vice is compliant with the HomePNA specification 1.0

and IEEE 802.3 specification.

The integrated HomePNA transceiver is a physical

layer device that enables data networking at speeds up

to 1 Mbps over existing residential phone wiring regard-

less of topology and without disrupting telephone

(POTS) service.

The integrated Ethernet transceiver is a physical layer

device suppor ting the IEEE 802.3 standard for

10BASE-T. It provides all of the PHY layer functions re-

quired to support 10 Mbps data transfer speeds. The

10BASE-T PHY suppor ts both half-duplex and

full-duplex operation.

PHY Data Interfaces

The Am79C901A PHY has both GPSI and MII-com-

patible data interfaces. In addition, a special mode,

GM_MODE, allows access to the MDC/MDIO com-

mand and control interface while in the GPSI mode.

For more information, see the Pin Descriptions and

the Detailed Functions sections.

Reset

There are two different types of RESET operations that

may be perfor med on the Am79C901A device,

H_RESET or S_RESET. The following is a description

of each type of RESET operation.

H_RESET

Hardware Reset (H_RESET) is a reset operation that

has been initiated by the proper asser tion of the

RESET pin of the Am79C901A device. When the

minimum pulse width timing as specified in the

RESET pin description has been satisfied, an inter-

nal reset operation will be performed.

H_RESET will program all of the registers to their

default value.

S_RESET

In a software reset (S_RESET), programming bit 15 of

HPR0 to 1 will reset all the registers in the 1 Mbps

HomePNA PHY (HPRs), and programming bit 15 of

TBR0 to 1 will reset TBR4, TBR7, TBR17, and TBR24

in the 10BASE-T PHY. These bits are self-clearing.

DETAILED FUNCTIONS

GPSI Interface

The seven signals that comprise the GPSI are TXCLK,

TXEN, TXDAT, RXCLK, RXCRS, RXDAT, and CLS. Of

these, only TXEN and TXDAT are inputs to the PHY;

the other five are outputs from the PHY. These signals

behave differently depending on which operation is cur-

rently happening in the PHY. The operations of the

PHY are as follows: Idle (no activity in either direction),

RXPKT (receiving data), and TXPKT (transmitting

data). The subsequent subsections analyze each

GPSI-related state of the PHY in detail.

Figure 1.

Idle State

TXCLK

TXEN

TXDAT

RXCLK

RXCRS

RXDAT

CLS

Note: RXCLK and TXCLK are synchronized to the same phase. All other signals are inactive. The two clock

signals toggle for an overall period of 583.3ns (about 1.7 MHz).

22304B-3

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