AM79C901AVCT datasheet(41/90 Pages) AMD

41 / 90 page

Am79C901A

PR ELI M IN AR Y

Instruction Register and Decoding Logic

After the TAP FSM is reset, the IDCODE instruction is

always invoked. The decoding logic gives signals to con-

trol the data flow in the data registers according to the

current instruction.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial

Shift Stage and the Parallel Output Stage, respectively.

There are four possible operation modes in the BSR

cell shown in Table 13.

Other Data Registers

Other data registers are the following:

1. Bypass register (1 bit)

2. Device ID register (32 bits) (Table 14).

Boundary Scan Cells

In Boundary Scan, most of the chip input and output

latches are linked together to form a scan chain.

The main purpose of this is board-level testing. See

Table 15.

To force the output pins, use SAMPLE to load the

BSR cells via the TDI pin and EXTEST to force the

output. Program the output cells, and set the control

cells to enable the output, or clear the control cells to

float the output.

To sample the chip inputs and outputs, use a SAMPLE

command and cell values are shifted out through the

TDO pin. Check the values in the input cells. Both input

and output pins have input-type cells.

Table 15.

Boundary Scan Ring Order

Table 12.

IEEE 1149.1 Supported Instruction

Summary

Instruction

Name

Instruction

Code

Description

Mode

Selected

Data

EXTEST

0000

External Test

Test

BSR

IDCODE

0001

ID Code

Inspection

Normal

ID REG

SAMPLE

0010

Sample

Boundary

Normal

BSR

TRI_ST

0011

Force Tri-

State

Normal

Bypass

BYPASS

1111

Bypass Scan Normal

Bypass

TRI_ST

0011

Force Tri-

State

Normal

Bypass

BYPASS

1111

Bypass Scan Normal

Bypass

Table 13.

BSR Mode Of Operation

Capture

Shift

Update

System Function

Table 14.

Device ID Register

Bits 31-28

Version

Bits 27-12

Part Number (1001 0000 0001 0000)

Bits 11-1

Manufacturer ID. The 11-bit manufacturer ID

code for AMD is 00000000001 in

accordance with JEDEC publication 106-A.

Bit 0

Always a logic 1

BSR Cell

No.

Cell Name

Cell

Type1

No.

XTAL_SEL_L

CRS

OUT

CRS_COL_OEN

–

COL

OUT

TXD3_CSN

TXD2

TXD1_SDI

TXD0_TXDAT

TX_EN

TX_CLK_OEN

–

TX_CLK

OUT

GM_MODE

RX_ER

OUT

PHY_SEL

RX_CLK

OUT

RX_DV_RXEN

OUT

RXD_OEN

–

RXD0_RXDAT

OUT

RXD1

OUT

RXD2

OUT

RXD3

OUT

LED_SPEED

OUT

LED_POWER

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