AM79C901AVCT datasheet(55/90 Pages) AMD

55 / 90 page

Am79C901A

PR ELI M IN AR Y

HPR28: HomePNA PHY ISBI Control Register (Register 28)

Table 36.

HPR28: HomePNA PHY ISBI Control Register (Register 28)

HPR29: HomePNA PHY TX Control Register

(Register 29)

Table 37.

HPR29: HomePNA PHY TX Control Register (Register 29)

HPR30: HomePNA PHY Drive Level Control Register (Register 30)

Table 38.

HPR30: HomePNA PHY Drive Level Control Register (Register 30)

Bits

Name

Description

Read/

Write

Default

Value

(hex)

15:8

ISBI_SLOW

This value defines the number of TCLKs (116.6 ns)

separating data pulses for Symbol 0 in low-speed

mode.

R/W

7:0

ISBI_FAST

This value defines the number of TCLKs (116.6 ns)

separating data pulses for Symbol 0 in high-speed

mode.

R/W

Bits

Name

Description

Read/

Write

Default

Value

(hex)

15:8

TX_PULSE_WIDTH

This value defines the duration of a transmit pulse in

OSC cycles (16.7 ns). This will effectively determine

the transmit spectrum of the PHY.

R/W

7:4

TX_PULSE_CYCLES_N

This value defines the number of pulses that will be

driven onto the HRTXRX_N pin.

R/W

3:0

TX_PULSE_CYCLES_P

This value defines the number of pulses that will be

driven onto the HRTXRX_P pin.

R/W

Bits

Name

Description

Read/

Write

Default

Value

(hex)

15:12

Reserved

Reserved. Must be written as 0. Read = X.

RXX

11:6

High Level Control

Defines the drive level that will be utilized in the High

Power mode.

R/W

5:0

Low Level Control

Defines the drive level that will be utilized in the Low

Power mode.

R/W

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