AM79C901AVCT datasheet(20/90 Pages) AMD

20 / 90 page

Am79C901A

PR ELI M IN AR Y

RXD[3:0]

Receive Data

Output

RXD[3:0] is the nibble-wide receive data bus. Data

on R X D[ 3: 0 ] is dr iven on t he fa lling edge of

RX_CLK. RXD[3:0] should be ignored while RX_DV

is deasserted.

RX_DV

Receive Data Valid

Output

RX_DV is an output used to indicate that valid received

data is being presented on the RXD[3:0] pins and

RX_CLK is synchronous to the receive data. RX_DV

will be asserted prior to the RX_CLK rising edge, when

the first nibble of the Start of Frame Delimiter (SFD) is

driven on RXD[3:0], and will remain asserted until after

the rising edge of RX_CLK, when the last nibble of the

CRC is driven on RXD[3:0]. RX_DV will be deasserted

prior to the RX_CLK rising edge which follows this final

nibble. RX_DV transitions are driven on the falling edge

of RX_CLK.

CRS

Carrier Sense

Output

The CRS pin is active during receive or transmit activity

for the HomePNA PHY or during receive (based on

TBR17, bit 2) for the 10BASE-T PHY.

COL

Collision

Output

This signal is asserted whenever a collision is detected

on the transmit and receive path of the selected port.

This signal will also be asserted for ~1

µs within 40 µs

after the negation of the TXEN signal in support of the

SQE test. The SQE functionality may be controlled via

TBR17, bit 11, and HPR16, bit 12.

RX_ER

Receive Error

Output

RX_ER is an output for the 10BASE-T PHY that indi-

cates that the transceiver device has detected a coding

error in the receive data frame currently being trans-

ferred on the RXD[3:0] pins. RX_ER is ignored while

RX_DV is deasserted. Special code groups generated

on RXD while RX_DV is deasserted are ignored (e.g.,

bad SSD in TX and idle in T4). RX_ER transitions are

synchronous to RX_CLK.

TX_CLK

Transmit Clock

Output

TX_CLK is a clock output that provides the timing ref-

erence for the transfer of the TXD[3:0] and TX_ER sig-

nals from the Am79C901A device. TX_CLK provides a

nibble rate clock.

TXD[3:0]

Transmit Data

Input

TXD[3:0] is the nibble-wide data bus. Valid data is gen-

erated on TXD[3:0] on every rising edge of TX_CLK

while TX_EN is asserted. While TX_EN is deasserted,

TXD[3:0] values are ignored. TXD[3:0] transitions are

latched on the falling edge of TX_CLK.

TX_EN

Transmit Enable

Input

TX_EN indicates that the MAC device is presenting

valid transmit data on the TXD[3:0] bus. TX_EN must

be asserted with the first nibble of preamble and re-

mains asserted throughout the duration of the packet

until it is deasserted prior to the first TX_CLK following

the final nibble of the frame. TX_EN transitions are

latched on the falling edge of TX_CLK.

MDC

Management Data Clock

Input

MDC is the non-continuous clock input that provides a

timing reference for bits on the MDIO pin. During MII

management port operations, MDC runs at a nominal

frequency of 2.5 MHz.

MDIO

Management Data Input/Output

Input/Output

MDIO is a bidirectional MII management port data pin.

MDIO is an input during the header portion of the man-

agement frame transfers and during the data portion of

write operations. MDIO is an output during the data

portion of read operations.

The MDIO pin should be externally pulled up to VDD

with a 1.5 k

Ω ±5% resistor.

IEEE 1149.1 (JTAG) Test Access Port

Interface

TCK

Test Clock

Input

TCK is the clock input for the boundary scan test

mode operation. It can operate at a frequency of up to

10 MHz. TCK has an internal pull-up resistor.

TDI

Test Data In

Input

TDI is the test data input path to the Am79C901A PHY.

The pin has an internal pull-up resistor.

TDO

Test Data Out

Output

TDO is the test data output path from the Am79C901A

PHY. The pin is tri-stated when the JTAG port is inactive.

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