AM79C901AVCT datasheet(40/90 Pages) AMD

40 / 90 page

Am79C901A

PR ELI M IN AR Y

Auto-Negotiation goes further by providing a mes-

sage-based communication scheme called Next

Pages before connecting to the Link Partner.

Soft Reset Function

The PHY Control Register (TBR0) incorporates the soft

reset function (bit 15). It is a read/write register and is

self-clearing. Writing a 1 to this bit causes a soft reset.

When read, the register returns a 1 if the soft reset is

still being performed; otherwise, it is cleared to zero.

Note that the register can be polled to verify that the

soft reset has terminated. Under normal operating con-

ditions, soft reset will be finished in 150 clock cycles.

Soft reset only resets the 10BASE-T PHY unit registers

to default values (some register bits retain their previ-

ous values). Soft reset does not reset the management

interface.

10BASE-T Loopback

The 10BASE-T PHY is capable of supporting two dif-

ferent types of loopback, referred to as internal and

external loopback.

Internal Loopback

In internal loopback, the transmitted data is returned to

the receive data bus without transmitted data appear-

ing on the network. The MAC must be programmed to

support full-duplex operation and is responsible for

comparing the transmitted data to that received. Inter-

nal loopback is accomplished by setting the “enable

loopback mode” in TBR0, bit 14, to 1.

External Loopback

External loopback is accomplished by the use of an ex-

t e r nal shor ti ng plug. In t h is environm ent , t h e

10BASE-T PHY is left in through mode (i.e., enable

loopback mode in TBR0 = 0), the MAC in full duplex.

The transmitted data will then be looped back at the

shorting plug into the receive circuitry and driven onto

the receive data bus for the MAC to process and verify.

LED Support

The controller can support up to five LEDs. LED out-

put s LE D_COL , L E D _ AC TI VIT Y, LE D_LI NK ,

LED_SPEED, and LED_POWER allow for direct con-

nection of an LED and its supporting pull-up device.

The outputs are stretched to allow the human eye to

recognize even short events that last only several mi-

croseconds. The five LED outputs are configured as

shown in Table 11.

Table 11.

LED Default Configuration

IEEE 1149.1 (JTAG) Test Access Port

Interface

An IEEE 1149.1-compatible boundary scan Test Ac-

cess Port is provided for board-level continuity test and

diagnostics. All digital input, output, and input/output

pins are tested. The following paragraphs summarize

the IEEE 1149.1-compatible test functions imple-

mented in the controller. Refer to the IEEE 1149.1

Boundary Scan Architecture document for details.

Boundary Scan Circuit

The boundary scan test circuit requires four pins (TCK,

TMS, TDI, and TDO), defined as the Test Access Port

(TAP). It includes a finite state machine (FSM), an in-

struction register, a data register array, and a power-on

reset circuit. Internal pull-up resistors are provided for

the TDI, TCK, and TMS pins.

TAP Finite State Machine

The TAP engine is a 16-state FSM driven by the Test

Clock (TCK) and the Test Mode Select (TMS) pins. An

independent power-on reset circuit is provided to en-

sure that the FSM is in the TEST_LOGIC_RESET state

at power-up. Therefore, the TRST is not provided. The

FSM is also reset when TMS and TDI are high for five

TCK periods.

Supported Instructions

In addition to the minimum IEEE 1149.1 requirements

(BYPASS, EXTEST, and SAMPLE instructions), two

additional instructions (IDCODE and TRI_ST) are

provided to further ease board-level testing. All unused

instruction codes are reserved. See Table 12 for a sum-

mary of supported instructions.

LED Output

Indication

Driver

Mode

Pulse

Stretch

LED_COL

Collision

Open Drain

- Active Low

Enabled

LED_ACTIVITY

Activity

Open Drain

- Active Low

Enabled

LED_LINK

Link

Open Drain

- Active Low

Not

applicable

LED_SPEED

Speed

Open Drain

- Active Low

Not

applicable

LED_POWER

Power

Open Drain

- Active Low

Not

applicable

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