ADF7021

Preliminary Technical Data

Rev. PrI | Page 28 of 44

REGISTER 0—N REGISTER

TR1

TRANSMIT/

RECEIVE

0

TRANSMIT

RECEIVE

1

M3

M2

M1

MUXOUT

0

REGULATOR READY (DEFAULT)

0

END OF CAL

0

DIGITAL LOCK DETECT

0

RSSI READY

1Tx_Rx

1

LOGIC ZERO

1

THREE STATE

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

LOGIC ONE

U1

UART MODE

0DISABLED

1

ENABLED

N8

N7

N6

N5

N4

N3

N2

N1

N COUNTER

DIVIDE RATIO

031

032

.

.

.

1

253

1

254

1

0

0

.

.

.

1

1

1

0

1

.

.

.

.

.

.

1

1

1

1

0

1

1

1

.

.

.

1

0

1

1

1

.

.

.

1

0

1

1

1

.

.

.

1

0

0

1

1

.

.

.

.

.

.

1

0

1

0

1

255

15-BIT FRACTIONAL-N

8-BIT INTEGER-N

MUXOUT

ADDRESS

BITS

FRACTIONAL

DIVIDE RATIO

0

1

2

.

.

.

32764

32765

32766

32767

M15

0

0

0

.

.

.

1

1

1

1

M14

0

0

0

.

.

.

1

1

1

1

M13

0

0

0

.

.

.

1

1

1

1

...

...

...

...

...

...

...

...

...

...

...

M3

0

0

0

.

.

.

1

1

1

1

M2

0

0

1

.

.

.

0

0

1

1

M1

0

1

0

.

.

.

0

1

0

1

Figure 32.

Register 0—N Register Comments

•

RF Output Frequency

Direct output:

⎟

⎠

⎞

⎜

⎝

⎛

+

×

=

15

2

_

_

N

Fractional

N

Integer

PFD

RF

OUT

Divide-by-2 selected:

⎟

⎠

⎞

⎜

⎝

⎛

+

×

×

=

15

2

_

_

5

.

0

N

Fractional

N

Integer

PFD

RF

OUT

•

In UART mode, the DATA CLK | TxDATA pin is used to input the Tx data. The Rx Data is available on the DATA I/O | RxDATA pin.

•

MUXOUT

END OF CAL (Active High): Indicates when a fine IF filter calibration has finished.

DIGITAL LOCK DETECT (Active High): Indicates when the PLL has locked.

RSSI READY (Active High): Indicates RSSI signal has settled and RSSI readback can be performed.

Tx_Rx: Gives the status of Bit DB27 in this register. Can be used to control an external Tx/Rx switch.