ADF7021 datasheet(19/44 Pages) AD

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Preliminary Technical Data

ADF7021

Rev. PrI | Page 19 of 44

RSSI/AGC

The RSSI is implemented as a successive compression log amp

following the base band channel filtering. The log amp achieves

±3 dB log linearity. It also doubles as a limiter to convert the

signal-to-digital levels for the FSK demodulator. Offset

correction is achieved using a switched capacitor integrator in

feedback around the log amp. This uses the BB offset clock

divide. The RSSI level is converted for user readback and

digitally controlled AGC by an 80-level (7-bit) flash ADC. This

level can be converted to input power in dBm.

IFWR

LATCH

AAA

CLK

ADC

OFFSET

CORRECTION

RSSI

FSK

DEMOD

Figure 20. RSSI Block Diagram

RSSI Thresholds

When the RSSI is above AGC_HIGH_THRESHOLD, the gain

is reduced. When the RSSI is below AGC_LOW_THRESHOLD,

the gain is increased. A delay (AGC_DELAY) is programmed to

allow for settling of the loop. All of these parameters are set in

(defaults 30 and 70) and the delay value (default 10). The

default AGC setup values should be adequate for most

applications. The threshold values must be chosen to be more

than 30 apart for the AGC to operate correctly.

Offset Correction Clock

In Register 3, the user should set the BB Offset Clock Divide

Bits R3_DB[4:5] to give an offset clock between 1 MHz and 2

MHz:

BBOS_CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE)

where:

BBOS_CLK_DIVIDE can be set to 4, 8, or 16.

AGC Information and Timing

AGC is selected by default and operates by selecting the

appropriate LNA and filter gain settings for the measured RSSI

level. It is possible to disable AGC by writing to Register 9 if the

user wants to enter one of the modes listed in Table 8. The time

for the AGC circuit to settle and therefore, the time it takes to

measure the RSSI accurately, is typically 150 μs. However, this

depends on how many gain settings the AGC circuit has to

cycle through. After each gain change, the AGC loop waits for a

programmed time to allow transients to settle. This wait time

can be altered to speed up the settling by adjusting the

appropriate parameters.

XTAL

DIVIDE

CLK

SEQ

Delay

AGC

Time

Wait

AGC

where:

AGC Settling = AGC_Wait_Time × Number of Gain Changes

Thus, in the worst-case scenario, if the AGC loop has to go

through all five gain changes,

AGC_Delay =10 cycles

SEQ_CLK = 200 kHz

AGC Settling = 10 × 5 μs × 5 = 250 μs

Minimum AGC_Wait_Time must be at least 25 μs.

RSSI Formula (Converting to dBm)

Input_Power [dBm] = −120 dBm +

(Readback_Code + Gain_Mode_Correction) × 0.5

where:

Readback_Code is given by Bit RV7 to Bit RV1 in the readback

Gain_Mode_Correction is given by the values in Table 9.

LNA gain (LG2, LG1) and filter gain (FG2, FG1) are obtained

from Register 9.

Table 9. Gain Mode Correction

LNA Gain

(LG2, LG1)

Filter Gain

(FG2, FG1)

Gain Mode

Correction

H (1, 0)

TBD

H (1, 0)

M (0, 1)

TBD

M (0, 1)

TBD

L (0, 0)

M (0,1)

TBD

L (0, 0)

TBD

An additional factor should be introduced to account for losses

in the front-end-matching network/antenna.

FSK DEMODULATORS ON THE ADF7021

There are four demodulators on the ADF7021:

•

2FSK correlator/demodulator

•

2FSK linear demodulator

•

3FSK demodulator

•

4FSK demodulator

Select these using the Demod Scheme Bits, R4_DB[4:6].

FSK CORRELATOR/DEMODULATOR

The quadrature outputs of the IF filter are first limited and then

fed to a pair of digital frequency correlators that perform band-

pass filtering of the binary FSK frequencies at (IF + FDEV) and

(IF − FDEV). Data is recovered by comparing the output levels

from each of the two correlators. The performance of this

frequency discriminator approximates that of a matched filter

detector, which is known to provide optimum detection in the

presence of AWGN.

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