ADF7021 datasheet(25/44 Pages) AD

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Preliminary Technical Data

ADF7021

Rev. PrI | Page 25 of 44

2.0mA

3.65mA

14mA

TIME

REG.

READY

WR1

VCO

WR3

WR0

WR4

11mA TO

30mA

tOFF

tON

XTAL

TRANSMIT DATA

t15

Figure 27. Tx Programming Sequence and Timing Diagram

Table 14. Power-Up Sequence Description

Parameter

Value

Description/Notes

Signal to Monitor

2 ms typ

Crystal starts power-up after CE is brought high. This typically depends on the

specified crystal type and load capacitance.

CLKOUT

10 μs

Time for regulator to power up. The serial interface can be written to after this time.

MUXOUT

1ms typ

Variable delay that depends on XTAL settling and VCO settling. Should be set

so that VCO and XTAL finish settling at the same time, thus minimizing current

consumption.

T3, T5,T6, T7,

T9, T10

32 × 1/SPI_CLK

Time to write to a single register. Maximum SPI_CLK is 25 MHz.

1 ms

The VCO can power up in parallel with the crystal. This depends on the CVCO

capacitance value used. A value of 22 nF is recommended as a trade-off

between phase noise performance and power-up time.

CVCO pin

3.2 ms

IF filter coarse and fine calibration times. A coarse calibration typically takes

200 μs, while a fine calibration typically takes 3 ms (see the settings in the

T11

150 μs

This depends on the number of gain changes the AGC loop needs to cycle

through and AGC settings programmed. This is described in more detail in the

AGC Information and Timing section.

Analog RSSI on TEST_A

pin (available by writing

0x0B00 000F)

T12

5 × Bit_Period

This is the time for the clock and data recovery circuit to settle. This typically

requires 5-bit transitions to acquire sync and is usually covered by the preamble.

T13

20 × Bit_Period

This is the time for the automatic frequency control circuit to settle. This

typically requires 16-bit transitions to acquire lock and is usually covered by an

appropriate length preamble.

T14, T15

Packet length

Number of bits in payload by the bit period.

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