ADF7021 datasheet(13/44 Pages) AD

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Preliminary Technical Data

ADF7021

Rev. PrI | Page 13 of 44

VCO

4\N

THIRD-ORDER

Σ-Δ MODULATOR

PFD/

CHARGE

PUMP

4\R

INTEGER-N

FRACTIONAL-N

REFERENCE IN

Figure 10. Fractional-N PLL

The combination of the integer-N (maximum = 255) and the

fractional-N (maximum = 32768/32768) give a maximum N

divider of 255 + 1. Therefore, the minimum usable PFD is

[]

()

255

Frequency

Output

Required

Maximum

PFD

MIN

For example, when operating in the European 868 MHz to

870 MHz band, PFDMIN equals 3.4 MHz.

Voltage Regulators

The ADF7021 contains four regulators to supply stable voltages

to the part. The nominal regulator voltage is 2.3 V. Each

regulator should have a 100 nF capacitor connected between

CREG and GND. When CE is high, the regulators and other

associated circuitry are powered on, drawing a total supply

current of 2 mA. Bringing the CE pin low disables the

regulators, reduces the supply current to less than 1 μA, and

erases all values held in the registers. The serial interface

operates from a regulator supply; therefore, to write to the part,

the user must have CE high and the regulator voltage must be

stabilized. Regulator status (CREG4) can be monitored using

the regulator ready signal from muxout.

MUXOUT

The MUXOUT pin allows the user to access various digital

points in the ADF7021. The state of MUXOUT is controlled by

Bits R0_DB[29:31].

Regulator Ready

Regulator ready is the default setting on MUXOUT after the

transceiver is powered up. The power-up time of the regulator is

typically 50 μs. Because the serial interface is powered from the

regulator, the regulator must be at its nominal voltage before the

ADF7021 can be programmed. The status of the regulator can

be monitored at MUXOUT. When the regulator ready signal on

MUXOUT is high, programming of the ADF7021 can begin.

REGULATOR READY (DEFAULT)

DIGITAL LOCK DETECT

RSSI READY

Tx_Rx

LOGIC ZERO

TRISTATE

MUX

CONTROL

DGND

DVDD

MUXOUT

FILTER CAL COMPLETE

LOGIC ONE

Figure 11. MUXOUT Circuit

Filter Cal Complete

MUXOUT can be set to filter cal complete, which is active high.

This indicates when a fine filter calibration has been completed.

It can be used as an interrupt to a microcontroller.

Digital Lock Detect

Digital lock detect indicates when the PLL has locked. The lock

detect circuit is located at the PFD. When the phase error on

five consecutive cycles is less than 15 ns, lock detect is set high.

Lock detect remains high until a 25 ns phase error is detected at

the PFD.

RSSI Ready

MUXOUT can be set to RSSI ready. This indicates that the

internal analog RSSI has settled and a digital RSSI readback can

be performed.

TX_RX

TX_RX signifies whether the ADF7021 is in transmit or receive

mode. When in transmit ,mode, this signal is low. When in

receive mode, this signal is high. It can be used to control an

external Tx/Rx switch.

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