ADF7021 datasheet(27/44 Pages) AD

27 / 44 page

Preliminary Technical Data

ADF7021

Rev. PrI | Page 27 of 44

SERIAL INTERFACE

The serial interface allows the user to program the 16, 32-bit

registers using a 3-wire interface (SCLK, SDATA, and SLE). It

consists of a level shifter, 32-bit shift register, and 16 latches.

Signals should be CMOS-compatible. The serial interface is

Data is clocked into the register, MSB first, on the rising edge of

each clock (SCLK). Data is transferred to one of 16 latches on

the rising edge of SLE. The destination latch is determined by

the value of the four control bits (C4 to C1). These are the

bottom 4 LSBs, DB3 to DB0, as shown in Figure 2. Data can also

be read back on the SREAD pin.

READBACK FORMAT

The readback operation is initiated by writing a valid control

word to the readback register and setting the readback-enable

bit (R7_DB8 = 1). The readback can begin after the control

word has been latched with the SLE signal. SLE must be kept

high while the data is being read out. Each active edge at the

SCLK pin clocks the readback word out successively at the

SREAD pin, as shown in Figure 31, starting with the MSB first.

The data appearing at the first clock cycle following the latch

operation must be ignored.

AFC Readback

The AFC readback is valid only during the reception of FSK

signals with either the linear or correlator demodulator active.

The AFC readback value is formatted as a signed 16-bit integer

comprised of Bit RV1 to Bit RV16, and is scaled according to

the following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/218

In the absence of frequency errors, the FREQ_RB value is equal

to the IF frequency of 100 kHz. Note that for the AFC readback

to yield a valid result, the down converted input signal must not

fall outside the bandwidth of the analog IF filter. At low-input

signal levels, the variation in the readback value can be

improved by averaging.

RSSI Readback

The RSSI readback operation yields valid results in Rx mode

with ASK or FSK signals. The format of the readback word is

shown in Figure 31. It is comprised of the RSSI level informa-

tion (Bit RV1 to Bit RV7), the current filter gain (FG1, FG2),

and the current LNA gain (LG1, LG2) setting. The filter and

LNA gain are coded in accordance with the definitions in

averaging of the measured RSSI values improves accuracy. The

input power can be calculated from the RSSI readback value as

outlined in the RSSI/AGC.

Battery Voltage ADCIN/Temperature Sensor Readback

The battery voltage is measured at Pin VDD4. The readback

information is contained in Bit RV1 to Bit RV7. This also

applies for the readback of the voltage at the ADCIN pin and

the temperature sensor. From the readback information, the

battery or ADCIN voltage can be determined using

VBATTERY = (Battery_Voltage_Readback)/21.1

VADCIN = (ADCIN_Voltage_Readback)/42.1

Silicon Revision Readback

The silicon revision readback word is valid without setting any

other registers, especially directly after power-up. The silicon

revision word is coded with four quartets in BCD format. The

product code (PC) is coded with three quartets extending from

Bit RV5 to Bit RV16. The revision code (RV) is coded with one

quartet extending from Bit RV1 to Bit RV4. The product code

for the ADF7021 should read back as PC = 0x210. The current

revision code should read as RC = 0x2.

Filter Calibration Readback

The filter calibration readback word is contained in Bit RV1 to

Bit RV8, and is for diagnostic purposes only. Using the automatic

filter calibration function (accessible through Register 5 and

decimal 32 should be read back.

READBACK MODE

AFC READBACK

DB15

RV16

RSSI READBACK

BATTERY VOLTAGE/ADCIN/

TEMP. SENSOR READBACK

SILICON REVISION

FILTER CAL READBACK

READBACK VALUE

DB14

RV15

DB13

RV14

DB12

RV13

DB11

RV12

DB10

RV11

LG2

RV11

DB9

RV10

LG1

RV10

DB8

RV9

FG2

RV9

DB7

RV8

FG1

RV8

DB6

RV7

DB5

RV6

DB4

RV5

DB3

RV4

DB2

RV3

DB1

RV2

DB0

RV1

Figure 31. Readback Value Table

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