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DA9062 датащи(PDF) 92 Page - Renesas Technology Corp

номер детали DA9062
подробное описание детали  PMIC for Applications Requiring up to 8.5 A
PDF  101 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA9062 датащи(HTML) 92 Page - Renesas Technology Corp

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DA9062
PMIC for Applications Requiring up to 8.5 A
Datasheet
Revision 3.8
15-Feb-2022
CFR0011-120-00
92 of 99
© 2022 Renesas Electronics
A.3
PAGE 2
A.3.1
Customer Trim and Configuration
Table 131: INTERFACE (0x105)
Field
Bit
Type
Description
IF_BASE_ADDR
7:4
R
Note 1
2-wire slave address MSBs. The LSBs of the slave address are
“000”. The complete slave address is then IF_BASE_ADDR * 23.
However, the device also responds to IF_BASE_ADDR * 23+1.
Reserved
3:0
·
R
Reserved
Note 1
The interface configuration can be written/modified only for unmarked samples which do not have the
control OTP_APPS_LOCK asserted/fused.
Table 132: CONFIG_A (0x106)
Field
Bit
Type
Description
Reserved
7:7
R
Reserved
PM_IF_HSM
6:6
R/W
2-wire interface permanently in high speed mode
PM_IF_FMP
5:5
R/W
2-wire interface selects fast mode+ timings
PM_IF_V
4:4
R/W
2-wire supplied from VDDCORE (0) / VDDIO (1).
IRQ_TYPE
3:3
R/W
nIRQ is active low (0) / high (1).
PM_O_TYPE
2:2
R/W
nRESET and nIRQ are push pull (0) / open-drain (1).
Reserved
1:1
R/W
Reserved
PM_I_V
0:0
R/W
nRESETREQ, SYS_EN, PWR_EN and KEEPACT supplied from
VDDCORE (0) / VDDIO (1).
Table 133: CONFIG_B (0x107)
Field
Bit
Type
Description
Reserved
7:7
R/W
Reserved
VDD_HYST_ADJ
6:4
R/W
nVDD_FAULT comparator hysteresis from 100 mV (0x0) to 450
mV (0x7) in 50 mV steps.
VDD_FAULT_ADJ
3:0
R/W
nVDD_FAULT comparator level from 2.5 V (0x0) to 3.25 V (0xF) in
50 mV steps.
Table 134: CONFIG_C (0x108)
Field
Bit
Type
Description
Reserved
7:7
R/W
Reserved
BUCK3_CLK_INV
6:6
R/W
Invert Buck3 clock polarity.
Reserved
5:5
R/W
Reserved
BUCK4_CLK_INV
4:4
R/W
Invert Buck4 clock polarity.
BUCK1_CLK_INV
3:3
R/W
Invert Buck1 clock polarity with respect to Buck2.
BUCK_ACTV_DISCHRG
2:2
R/W
Enable active discharging of buck rails.
Reserved
1:0
R/W
Reserved



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