DA9062 datasheet(56/101 Pages) RENESAS

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DA9062

PMIC for Applications Requiring up to 8.5 A

Datasheet

Revision 3.8

15-Feb-2022

CFR0011-120-00

56 of 99

be configured to wait until the clock’s duty cycle is within the range 30 % to 70 %. The start is

configured from the DELAY_MODE register and the stabilization time is programmed in the

STABILIZATION_TIME register. OUT_CLOCK controls whether the clock feed to the OUT_32K

output (GPIO) is affected by the stabilization timer. The RTC_CLOCK register provides a similar

gating function for the clock feed to the internal RTC counter.

The clock feed to the OUT_32K output can be controlled with the power sequencer, as described in

Section 8.9.6. In addition, the clock output is one of the features that can be disabled in the

POWERDOWN mode, as described in Section 8.9.7. When the OUT32K_PAUSE register is set, the

clock output is disabled in POWERDOWN.

8.14 Internal Oscillator

An internal oscillator provides a nominal 6.0 MHz clock that is divided to 3.0 MHz for the buck

converters. The frequency of the internal oscillator is adjusted during the initial start-up sequence of

DA9062 to within 5 % of the nominal 6.0 MHz.

Some applications require that the software is able to modify the oscillator frequency at runtime, for

example to avoid interference effects caused by harmonics of the buck converter operating

frequency. This can be achieved by writing a non-zero value to register OSC_FRQ. This control is a

signed 4-bit value where each step changes the frequency by about 1.33 %, which gives a range

from -10.65 % (-8) to +9.33 % (+7).

The tolerance of this frequency will affect most absolute timer values and PWM repetition rates.

8.15 Watchdog

The watchdog provides system monitoring functionality. A watchdog timeout triggers shutdown to

POWERDOWN mode, signalled in register FAULT_LOG. The watchdog can also be configured to

control a secondary reset output in addition to nRESET. This requires that one of the GPIOs is

configured as a GPO, controlled by the sequencer. The assertion/de-assertion is used as a reset,

and the GPIO is configured as a sequencer controlled GPO. This way, after the watchdog triggers

the power-down, the reset output is asserted by the sequencer during the power-down sequence.

Once enabled, the watchdog cannot be stopped and it runs in ACTIVE mode (this feature can be

bypassed with an OTP configuration). The source clock of the watchdog is automatically chosen

between the 32 kHz clock generated from the crystal oscillator and an internally generated slow

frequency clock.

After a cold boot, the watchdog is activated when entering ACTIVE mode. This first watchdog kick is

required for DA9062 to move to the ACTIVE mode after a cold boot, as illustrated in Figure 21. After

the watchdog is activated, the host must kick the watchdog periodically within the watchdog period

programmed with the TWDSCALE register. An interrupt can be generated to warn the host processor

of the watchdog timeout. The time for the warning interrupt is half of the watchdog period.

The kick can be done by a register write to register WATCHDOG (register CONTROL_F) or with the

GPIO0 pin configured as a WDKICK input. With register WDG_MODE = 1, the behavior of the

WDKICK input is modified so that either a pulse or a permanently asserted input prevents a

watchdog timeout. In this mode the parameter tWDMIN is not applicable.

If the host processor fails to feed the watchdog, DA9062 asserts a fault bit and enters

POWERDOWN mode. The watchdog timeout can also be configured to assert a reset output. This

requires that one of the GPIOs is configured as a reset output and assigned to a power sequencer

step, see Section 8.9.

After each watchdog timeout a retry counter is decremented. If the retry counter reaches zero,

DA9062 will stay in POWERDOWN mode, as described in Section 8.8.4. The number of allowed

retries can be programmed in the NFREEZE register.

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