DA9062 datasheet(64/101 Pages) RENESAS

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DA9062

PMIC for Applications Requiring up to 8.5 A

Datasheet

Revision 3.8

15-Feb-2022

CFR0011-120-00

64 of 99

10.2.2

LDOs and Switched Mode Supplies

The placement of the distributed capacitors on the VSYS rail must ensure that all VDD inputs and

VSYS are connected to a bypass capacitor close to the pad. It is recommended placing at least two

1 µF capacitors close to the VDD_LDOx pads and at least one 10 µF close to the VDD_BUCKx pads.

Using a local power plane underneath the device for VSYS might be considered.

Transient current loops in the area of the switching converters should be minimized.

The common references (IREF, VREF) should be placed close to the device and cross-coupling to

any noisy digital or analog trace must be avoided.

Output capacitors of the LDOs can be placed close to the input pins of the supplied devices (remote

from the DA9062).

Care must be taken with trace routing to ensure that no current is carried on feedback lines of the

buck output voltages (VBUCK<x>).

The inductor placement is less critical since parasitic inductances have negligible effect.

10.2.3

32 kHz Crystal Oscillator

The crystal and its load capacitors should be placed as close as possible to the IC with short and

symmetrical traces.

The traces must be isolated from noisy signals, especially from clocked digital ones. Ideally the lines

should be buried between two ground layers, surrounded by additional ground traces.

10.2.4

Optimizing Thermal Performance

DA9062 features a ground paddle which should be connected with as many vias as possible to the

PCB’s main ground plane in order to achieve good thermal performance.

Solder mask openings for the landing pads must be arranged to prohibit solder flowing into vias.

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