DA9062 datasheet(43/101 Pages) RENESAS

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DA9062

PMIC for Applications Requiring up to 8.5 A

Datasheet

Revision 3.8

15-Feb-2022

CFR0011-120-00

43 of 99

8.6

LDOs

All LDOs employ Dialog Semiconductor SmartMirror

™ dynamic biasing technology, see Figure 19,

which maintains high performance over a wide range of operating conditions and a power saving

mode (SLEEP mode) to minimize the quiescent current during very low output current. The circuit

technique offers significantly higher gain bandwidth performance than conventional designs, enabling

higher power supply rejection performance at higher frequencies. PSRR is maintained across the full

operating current range however quiescent current consumption is scaled to demand improved

efficiency when current demand is low.

Figure 19: SmartMirrorTM Voltage Regulator

8.6.1

Control

The LDOs can be enabled by writing directly to a register bit (LDO<x>_EN), controlling it via a GPI,

see Section 8.3.1.1, or assigning it to a power sequencer step, see Section 8.9.3. Each LDO features

two voltage control registers (VLDO<x>_A/VLDO<x>_B) that allow two output voltage pre-

configurations. The active setting can then be selected either with a register bit (VLDO<x>_SEL), via

a GPI, see Section 8.3.1.1, or automatically based on the DA9062 power mode. The SLEEP mode of

the LDOs can be linked to either the A or B setting (LDO<x>_SL_A/LDO<x>_SL_B). Therefore, the

LDO will switch to SLEEP mode when the setting is active.

LDO1 differs from the other LDOs because it can be configured as an always-on regulator. This

means that it is also enabled in RESET mode, see Section 8.8.3.

8.6.2

Current Limit

Each LDO provides over-current detection. The current limit is fixed for each LDO based on their

current capability. If any of the LDOs’ current limit is exceeded for longer than 10 ms, an event,

E_LDO_LIM, is triggered. The status of the limit comparator can be observed from LDO<x>_ILIM

(register STATUS_D)

. If an LDO’s current limit is exceeded for longer than 200 ms, the LDO is

automatically disabled. This shutdown feature can be disabled by clearing the LDO_SD register.

Once disabled due to an over-current, the LDO must be re-enabled by one of the sources described

in Section 8.6.1.

8.6.3

Output Pull-Down

When over-voltage (1.06 * VLDO<x>) occurs, the voltage regulators enable an internal load to

discharge the output back to its configured voltage. This feature can be disabled in

LDO<x>_PD_DIS.

VOUT

COUT

ESR

VIN

VREF

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