DA9062 datasheet(37/101 Pages) RENESAS

37 / 101 page

DA9062

PMIC for Applications Requiring up to 8.5 A

Datasheet

Revision 3.8

15-Feb-2022

CFR0011-120-00

37 of 99

8.2.1

The 2-wire interface has direct access to two pages of the DA9062 register map (up to 256

addresses). The register at address zero on each page is used as a page control register (the LSB of

control PAGE is ignored). Writing to the page control register changes the active page for all

subsequent read/write operations unless an automatic return to page 0 is selected using register

REVERT. Unless REVERT was asserted after modifying the active page, it is recommended to read

back the page control register to ensure that future data exchange is accessing the intended

registers.

DA9062 also offers an alternative way to access register pages which avoids writing explicitly to

PAGE. DA9062 responds to multiple consecutive slave addresses and updates PAGE automatically

based on the slave address. For example, when IF_BASE_ADDR[7:4] = 0xB the slave address

changes PAGE as follows:

Slave address = 0xB0  PAGE = 0x00

Slave address = 0xB2  PAGE = 0x02

8.2.2

Details of the 2-Wire Protocol

All data is transmitted across the 2-wire bus in 8-bit groups. To send a bit, the SDA line is driven at

the intended state while the SCL is low. Once the SDA has settled, the SCL line is brought high and

then low. This pulse on SCL stores the SDA bit in the receiver’s shift register.

A 2-byte serial protocol is used: one address byte and one data byte. Data and address transfer

transmits the MSB first for both read and write operations. All transmissions begin with the START

condition from the master during which the bus is in IDLE state (the bus is free). It is initiated by a

high-to-low transition on the SDA line while the SCL is in high state. A STOP condition is indicated by

a low-to-high transition on the SDA line while the SCL is in high state. The START and STOP

conditions are illustrated in Figure 12.

START

STOP

SDA

SCL

Transaction

Figure 12: Timing of the START and STOP Conditions

DA9062 monitors the 2-wire bus for a valid slave address whenever the interface is enabled. It

responds immediately when it receives its own slave address. This is acknowledged by pulling the

SDA line low during the following clock cycle (white blocks marked with A in the following figures).

The protocol for a register write from master to slave consists of a START condition, a slave address,

a read/write-bit, 8-bit address, 8-bit data, and a STOP condition. DA9062 responds to all bytes with

an ACK. A register write operation is illustrated in Figure 13.

SLAVEadr

REGadr

DATA

S = START condition

A = Acknowledge (low)

P = STOP condition

W = Write (low)

Master to Slave

Slave to Master

7-bits

1-bit

8-bits

Figure 13: Byte Write Operation

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