DA9062 datasheet(41/101 Pages) RENESAS

41 / 101 page

DA9062

PMIC for Applications Requiring up to 8.5 A

Datasheet

Revision 3.8

15-Feb-2022

CFR0011-120-00

41 of 99

8.3.2

GPO Functionality

The outputs can be configured as push-pull or open-drain outputs, see Table 24. An internal pull-up

can be enabled/disabled from GPIO<x>_PUPD (open-drain mode). The GPIO<x>_MODE settings

can control the output state.

Instead of controlling the output with GPIO<x>_MODE, a selection of alternatives is available in the

GPIO<x>_OUT controls. These include: the forwarding function, see Section 8.3.4, the power supply

sequencer, see Section 8.9, the 32 kHz clock (OUT_32K), and the status of the supply voltage

supervision (nVDD_FAULT). When the GPIO is configured as an output and GPIO<x>_OUT is set to

0x0, the GPIO<x>_MODE determines the state of the output.

8.3.2.1

nVDD_FAULT

nVDD_FAULT gives the status of the system supply monitoring, see Section 8.11. The assertion of

nVDD_FAULT indicates that the main supply input voltage has been low (VSYS < VDD_FAULT_LOWER) for

more than 100 ms and informs the host processor that the power will shut down. It can be configured

to drive a GPO from the GPIO<x>_OUT controls. The driver type (push-pull, open-drain) selection

and pull-up resistor control function normally. The GPIO<x>_MODE can be used to invert the

incoming nVDD_FAULT signal.

8.3.2.2

OUT_32K

OUT_32K feeds a buffered 32 kHz clock signal that is derived from the internal oscillator. The signal

output buffer can be controlled either with the power sequencer or manually via EN_32KOUT, and

paused automatically during POWERDOWN mode with the OUT32K_PAUSE bit.

Glitch-free switching between a 32 kHz clock output and another GPIO configuration is not

guaranteed. Therefore, configuring a GPIO for 32 kHz clock output should only be done in OTP.

However, enabling and disabling the buffer is still dynamic as described above.

8.3.3

Alternate Functions

GPIO0, GPIO2, and GPIO4 can be used for alternate functions. These are digital control signals that

don’t employ the debouncing, event detection, or interrupt generation functions. Only the input buffer

of the GPIO block is employed. The alternate functions of DA9062 are listed in Table 25 and

described in the following subsections. A debouncing filter can be applied also on the alternate

functions with a configurable debouncing time (register DEBOUNCING).

Table 25: GPIO Alternate Input Functions

GPIO

Alternate Function

Description

GPIO0

WDKICK

Watchdog kick or disable

GPIO1

GPIO2

PWR_EN

Power mode control

GPIO3

GPIO4

SYS_EN

Power mode control

8.3.3.1

SYS_EN

SYS_EN (pin GPIO4) controls the SYSTEM_EN bit and thereby the power mode of DA9062. It is

part of the power supply sequencer functionality described in Section 8.9. SYS_EN is an edge-

sensitive signal and its polarity can be chosen in the GPIO4_TYPE register.

Asserting SYS_EN causes an interrupt (E_GPIx) and a wakeup event. De-asserting SYS_EN

triggers a power-down sequence but no interrupt.

DA9062 датащи(PDF) 41 Page - Renesas Technology Corp

DA9062 датащи(HTML) 41 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL