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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC574S60 датащи(PDF) 41 Page - STMicroelectronics |
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SPC574S60 датащи(HTML) 41 Page - STMicroelectronics |
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41 / 77 page  DS10601 Rev 6 41/77 SPC574Sx Electrical characteristics 76 Figure 10. ADC decoupling capacitance/resistance scheme Note: All 1.2V pins should be shorted externally on board with minimum resistance and minimum inductance. It is recommended to use a 1.2V plane on which all 1.2V pins are shorted to keep resistance and inductance negligible. Recommended capacitors should be placed very close to the device pins such that parasitic resistance can be reduced. Connection from VDD_LV pin to capacitor top plate should not exceed more than 5mohm in resistance and 0.5nH in inductance. Similarly connection from bottom plate of capacitor to PCB ground should not have more than 5mohm resistance and 0.5nH inductance. DEVICE VHV_ADC VREF_ADC INPUT CHANNEL VHV_ADC[1:0] VREF_ADC[1:0] Ce ADC channel[31:0] C2 C1 R2 Re 22 32 Table 22. ADC decoupling capacitance/resistance values Label Instances Value Recommended commercial components based on PVT/aging degradation C1 2 470 nF min 1 µF R2 2 5 to 8 Ω max 8 Ω C2 2 1 µF min 2.2 µF Ce 32 ≥ 8192(1) × Cs(2) × 2(3) = 115 nF min 200 nF Re 32 <= 1/(8192(1) × Fs × Cs(2) × 2(3))=13 Ω max 10 Ω 1. Factor depending on the ADC 12 bits 2. Input capacitance Cs = 7 pF 3. Factor for 2 ADCs on the same physical channel Table 23. Package ADC supply decoupling capacitance PAD eTQFP100 package VREFH_ADC_S0 36 VDD_HV_ADC_S0 39 VREFH_ADC_S1 — VDD_HV_ADC_E0 51 |
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