SPC574S60 datasheet(44/77 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC574Sx

44/77

DS10601 Rev 6

3.13

Platform Flash controller configuration

3.14

Flash memory electrical characteristics

Table 28 shows the program and erase characteristics.

TMS

Weak pull-up

—

TDI

Weak pull-up

—

TDO

High impedance

—

1. Refer to pinout information for terminal type

2. POWER-UP state is guaranteed from VDD_HV_IO >VDD_POR and maintained until supply crosses the power-on reset

thresholds VPORUP_LV for LV supply and VPORUP_HV for high voltage supply.

3. Before software configuration

4. Pull-down and pull-up strengths are provided in Table 13: I/O pull-up/pull-down DC electrical characteristics

5. Unlike ESR0, ESR1 is provided as a normal GPIO and implements weak pull-up during power-up.

6. An internal pull-down is implemented on the TESTMODE pin to prevent the device from entering test mode if the package

TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin to VSS_HV_IO on the board for

maximum robustness, but not required. The value of TESTMODE is latched at the negation of reset and has no affect

afterward. The device will not exit functional reset with the TESTMODE pin asserted during power-up. The TESTMODE pin

can be connected externally directly to ground without any other components.

Table 26. Functional terminals state during power-up and reset (continued)

TERMINAL

type(1)

POWER-UP(2)

pad state

RESET

pad state

DEFAULT

pad state(3)

Comments

Table 27. Wait states versus system clock frequency(1)

1. RWSC is a field in the Flash memory of the PFCR register used to specify the wait states for address

pipelining and read/write accesses.

Read Wait State Control (RWSC)

System clock frequency (MHz)(2)

2. Values to be confirmed by silicon validation.

0b00000

0 - 30 MHz

0b00001

30 - 60 MHz

0b00010

60 - 90 MHz

0b00011

90 - 121 MHz

0b00100

121 - 140 MHz

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