SPC574S60 datasheet(23/77 Pages) STMICROELECTRONICS

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DS10601 Rev 6

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SPC574Sx

Electrical characteristics

3.7

Thermal characteristics

3.7.1

Package thermal characteristics

3.7.2

Power considerations

An estimation of the chip junction temperature, TJ can be obtained from the equation:

Equation 1: TJ = TA + (RθJA × PD)

where:

TA = ambient temperature for the package (°C)

RθJA = junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards

to provide consistent values for estimations and comparisons. The difference between the

6. Core voltage as measured on device pin to guarantee published silicon performance.

7. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor

external supply voltage may result in erroneous operation of the device.

8. The IO rail #0 and #1 are independent only in external regulator mode. In internal regulator mode a single unique IO rail is

applicable. In the QFP100 package only the internal regulator mode is supported.

9. Full device lifetime without performance degradation.

10. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Table 6:

Absolute maximum ratings for maximum input current for reliability requirements.

11. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is

above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network

calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. For more

information, see the device characterization report.

Table 9. Thermal characteristics for eTQFP100

Symbol

Parameter

Boundary Conditions

Value

Unit

RθJA

Junction to ambient, natural convection(1)

Four layer board

2s2p board

°C/W

RθJB

Junction to board(2)

Four layer board

2s2p board

RθJCtop

Junction to top case(3)

1s board

Top cold plate

RθJCbottom

Junction to bottom case(4)

Bottom cold plate

1.1

ΨJT

PSI j-top-case, natural convection(5)

Operating conditions

0.6

1. JESD51-7

2. JESD51-8, ring cold plate

3. Thermal resistance between the die and the case top surface as measured by the cold plate best practice guidelines

(JESD51)

4. Thermal resistance between the die and the case bottom surface as measured by the cold plate best practice guidelines

(JESD51) without any interface resistance

5. Thermal characterization parameter, not properly a thermal resistance, indicating the temperature difference between

package top and the junction in operating conditions as per JESD51-2

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