25CSM04T-ISLASHMF datasheet(16/55 Pages) MICROCHIP

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25CSM04

DS20005817D-page 16

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4.5.3

WRITE-PROTECT PIN FUNCTION

While in both Legacy Write Protection mode and

Enhanced Write Protection mode, writing to the

STATUS register and the Memory Partition registers

can be inhibited by enabling the WPEN bit in the

STATUS register. When the WPEN function is enabled,

the contents of these registers will be protected when

the WP pin is asserted (low). In order for these

registers to be protected, the WP pin must be asserted

for the entire CS valid time. Details about the WPEN

function are provided in Section 6.1.1 “Write-Protect

Enable Bit”.

If the internal write cycle has already been initiated, WP

pin going low will have no effect on any write sequence.

The WP pin function is blocked when the WPEN bit in

the STATUS register is a logic ‘0’. This will allow the

user to install the 25CSM04 device in a system with the

WP pin tied to VSS and still be able to write to the

STATUS register. All WP pin functions are enabled

when the WPEN bit is set to a logic ‘1’.

4.5.4

FREEZE MEMORY PROTECTION

CONFIGURATION (FRZR)

The current state of the Memory Partition registers and

write protection mode can be permanently frozen so

that no further modification of their contents is possible.

This is accomplished by the use of the Freeze Memory

Protection Configuration (FRZR) instruction. For addi-

tional information on the Memory Partition registers,

refer to Section 10.0 “Memory Partition Functional-

ity”.

Before a FRZR instruction can be issued, first a WREN

instruction must be issued to set the WEL bit in the

STATUS register to a logic ‘1’, followed by a PRWE

instruction to set the PREL bit to a logic ‘1’ as well.

Once these two steps are complete, the FRZR instruc-

tion can be sent to the device.

To freeze the state of the Memory Protection

Configuration with the FRZR instruction, the CS pin

must be driven low, followed by sending an opcode of

37h to the device on the SI line. Next, an address of

AA40h is sent, followed by a confirmation data byte of

D2h. Upon deasserting the CS pin, the device will

begin a self-timed internal write cycle to set the FMPC

bit, freeze all eight Memory Partition registers and the

Write Protection Mode (WPM) bit in the STATUS

Once the write cycle is completed, the PREL bit and

WEL bit in the STATUS register will be reset back to the

logic ‘0’ state, the WPM STATUS register bit (bit 7, byte

1) will be permanently set to its current state and the

FMPC STATUS register bit (bit 5, byte 1) will be

permanently set to a logic ‘1’ to indicate that the

Memory Protection Configuration has been frozen. If

the registers and WPM bit have already been frozen,

any attempt to issue the FRZR instruction will be

ignored. The device will return to the Idle state once the

CS pin has been deasserted.

Note:

The Write-Protect Enable (WPEN) and

Block Protection (BP[1:0]) bits are not

affected by the FRZR instruction.

Note:

The FRZR instruction will be ignored if the

WPEN Bit (byte 0, bit 7) of the STATUS

is asserted.

Note:

Once the Memory Partition Registers and

WPM bit have been frozen, it will be

impossible to change their state.

Note:

If the CS pin is deasserted before the end

of the 40-bit sequence, the instruction will

be aborted and no write cycle will take

place.

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