25CSM04T-ISLASHMF datasheet(23/55 Pages) MICROCHIP

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DS20005817D-page 23

25CSM04

6.1.6

ERROR CORRECTION STATE

LATCH

The Error Correction State (ECS) bit is located in byte

1, bit 6 of the STATUS register. This bit indicates

whether the on-chip Error Correction Code (ECC) logic

scheme was invoked during the previous read

sequence. For more information related to ECC, refer

to Section 8.2 “Error Correction Code (ECC)

Architecture”.

The ECS bit will be set to logic ‘0’ unless the previously

executed read sequence required the use of the ECC

logic scheme. When this occurs the ECS bit will set to

logic ‘1’.

The ECS bit will continue to read a logic ‘1’ until another

read sequence occurs where the use of the ECC logic

scheme was not required, a Power-on Reset (POR)

event occurs, or a Software Device Reset (SRST)

instruction is sent to the 25CSM04.

6.1.7

FREEZE MEMORY PROTECTION

CONFIGURATION BIT

The Freeze Memory Protection Configuration (FMPC)

bit resides in byte 1, bit 5 of the STATUS register. This

bit is nonvolatile and One-Time-Programmable (OTP)

with a factory default value of a logic ‘0’.

This bit can only be set to a logic ‘1’ as a result of the

Freeze Memory Protection Configuration (FRZR)

instruction

(Section 4.5.4

“Freeze

Memory

Protection Configuration (FRZR)”). This bit cannot

be modified with a Write STATUS Register (WRSR)

instruction. Once this bit has been permanently set to a

logic ‘1’, the memory configuration cannot be changed.

6.1.8

PARTITION WRITE ENABLE LATCH

In addition to the WEL bit, enabling and disabling

writing to the Memory Partition register is done by

issuing the Set Memory Partition Write Enable Latch

(PRWE) as shown in Figure 10-3 and the Reset Memory

Partition Write Enable Latch (PRWD) as shown in

Figure 10-4. These functions change the status of the

PREL bit (byte 1, bit 4). in the STATUS register.

6.1.9

PARTITION ADDRESS BOUNDARY

PROTECTION BIT

The Partition Address Boundary Protection (PABP) bit

is located in byte 1, bit 3 of the STATUS register. This

bit can be read through an RDSR instruction but can

only be set or cleared through a Protect Partition

Address Boundary sequence (see Section 10.1.3

“Protecting the Partition Endpoint Addresses”).

When programmed to a Logic ‘1’, the address range

bits in the Memory Partition registers are read-only and

cannot be modified but the behavior bits can still be

modified.

If the Freeze Memory Protection Configuration bit has

been programmed to a logic ‘1’, the address range and

behavior bits are permanently read-only and cannot be

modified regardless of the state of the PABP bit.

Note:

The WEL bit must first be set before

issuing the PRWE instruction, otherwise it

is ignored.

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