25CSM04T-ISLASHMF datasheet(38/55 Pages) MICROCHIP

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25CSM04

DS20005817D-page 38

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10.2.2

MEMORY PARTITION REGISTER

WRITE DISABLE (PRWD)

A Partition Register Write Disable (PRWD) instruction is

also available (opcode 0Ah) which will reset the PREL

bit in the STATUS register to a logic ‘0’ state.

FIGURE 10-4:

PARTITION REGISTER WRITE DISABLE (PRWD) INSTRUCTION

10.2.3

WRITING TO THE MEMORY

PARTITION REGISTERS

Once the WEL and PREL bits in the STATUS register

have been set to ‘1’, the Memory Partition registers can

be programmed provided that the FMPC bit in the

STATUS register has not already been set to a logic ‘1’

by executing the FRZR sequence (Section 4.5.4

“Freeze

Memory

Protection

Configuration

(FRZR)”).

Writing to the MPRs uses the WMPR instruction. To

issue the WMPR instruction, the CS pin must first be

asserted and then the opcode 32h must be clocked into

the device on the SI line, followed by three address

bytes containing the Memory Partition register address

that corresponds with the desired Memory Partition

(Table 10-3).

Following the address information, a data byte using

the register definition shown in Register 10-1 must be

sent to the device followed by deasserting the CS line.

The device will enter an internal write cycle and once

complete, the WEL and PREL STATUS register bits are

automatically reset to logic ‘0’.

Any additional data clocked into the device after the

first byte of data will cause the instruction to be ignored

as only one MPR can be programmed at a time.

Termination of the sequence at somewhere other than

an 8-bit boundary will cause the instruction to be

ignored. This sequence is depicted in Figure 10-5.

The MPR Partition Endpoint Address values must be

loaded sequentially in each register as the eight MPRs

are decoded sequentially by the device, starting with

MPR0. If a higher order MPR sets a Partition Endpoint

Address less than or equal to the ending address of a

lower order MPR, that higher order MPR is ignored and

no behavior is set by its contents.

FIGURE 10-5:

WRITE MEMORY PARTITION REGISTERS (WMPR) SEQUENCE

SCK

High-Impedance

PRWD Opcode (0Ah)

MSb

High-Impedance

0 0 1 1 00

WMPR Opcode (32h)

Address Bits A23-A0

(MPR in A18-A16)(2)

XX X X

A18

D7 D6 D5 D4 D3 D2 D1 D0

Data In

MSb

XX X

SCK

234

567

9 10 11 12

833

TWC(1)

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

Address bits A23-A19 and A15-A0 are ignored.

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