25CSM04T-ISLASHMF datasheet(12/55 Pages) MICROCHIP

12 / 55 page

25CSM04

DS20005817D-page 12

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3.0

MEMORY ORGANIZATION

3.1

EEPROM Organization

The 25CSM04 is internally organized as 2,048 pages

of 256 bytes each.

3.2

Device Registers

The 25CSM04 contains four types of registers that

modulate device operation and/or report on the current

status of the device. These registers are:

• STATUS register

• Security register

• Memory Partition registers (eight total)

• Identification register

3.2.1

STATUS REGISTER

The STATUS register is a 16-bit combination of volatile

and nonvolatile bits. It is used to modify the write

protection functions as well as store various aspects of

the current status of the device. Details about the

STATUS register are covered in Section 6.0 “STATUS

3.2.2

SECURITY REGISTER

The Security register is split into a read-only section

and a user-programmable lockable ID page section.

The read-only section contains a preprogrammed,

globally unique, 128-bit serial number.

The user-programmable (lockable ID page) section of

the Security register is ideal for applications that need

to irreversibly protect critical or sensitive application

data from ever being altered. See Section 9.0

“Security Register” for more details about the

Security register.

3.2.3

MEMORY PARTITION REGISTERS

The 25CSM04 is equipped with eight Memory Partition

registers. Each register is an 8-bit nonvolatile register

which can be programmed with an ending address for

the partition as well as determine the behavior of that

partition. The partition protection can be set to one of

four levels:

•Unprotected

• Software write-protected

• Hardware write-protected by the WP pin

• Software write-protected with locked memory

partition register

A complete description of the Memory Partition register

function can be found in Section 10.0 “Memory

Partition Functionality”.

3.2.4

IDENTIFICATION REGISTER

The Identification register is a 40-bit nonvolatile,

read-only register that contains device identification

data in compliance with the JEDEC® standard for

“Manufacturer and Device ID Read Methodology for

SPI Compatible Serial Interface Memory Devices”. The

contents and format of the Identification register can be

reviewed in Section 11.1 “Reading the Identification

FIGURE 3-1:

MEMORY ORGANIZATION

Memory Address Range

Protection Features

4-Mbit

EEPROM

4-Kbit

Security

4-Mbit Address Range:

000000h–07FFFFh

128-bit Serial Number

Address Range

(000000h–00000Fh)

Legacy Write Protection

• Block Protection (BP bits in STATUS register)

• Hardware Write Protection

(WP pin via STATUS register)

Enhanced Write Protection

• User-Definable Memory Partitioning (WP Pin or

Software Write Protection)

Read-Only

Permanently Lockable by

Software

User-Programmable Lockable ID Page

Address Range (000100h–0001FFh)

Reserved for Future Use (FFh)

Address Range

(000010h–0000FFh)

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