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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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25CSM04T-I/MF датащи(PDF) 7 Page - Microchip Technology |
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25CSM04T-I/MF датащи(HTML) 7 Page - Microchip Technology |
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7 / 55 page  2019-2022 Microchip Technology Inc. and its subsidiares DS20005817D-page 7 25CSM04 FIGURE 1-5: HOLD TIMING TABLE 1-3: EEPROM CELL PERFORMANCE CHARACTERISTICS Operation Test Condition Minimum Maximum Units Write Endurance(1,2) TA = +25°C, 2.5V ≤ VCC ≤ 5.5V 1,000,000 — Write Cycles Data Retention(1) TA = +55°C 100 — Years Note 1: Performance is determined through characterization and the qualification process. 2: Due to the memory array architecture, the write cycle endurance is specified for write sequences in groups of four data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any integer (N) by four (i.e., 4*N). The end address can be found by adding three to the beginning value (i.e., 4*N+3). See Section 8.2 “Error Correction Code (ECC) Architecture” for more details on this implementation. CS SCK SO SI HOLD 17 16 16 17 19 18 Don’t Care 5 High-Impedance n + 2 n + 1 n n - 1 n n + 2 n + 1 n n n - 1 |
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