25CSM04 datasheet(14/55 Pages) MICROCHIP

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25CSM04

DS20005817D-page 14

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4.3

Device Opcodes

4.3.1

SERIAL OPCODE

After the device is selected by driving CS low, the first

byte sent must be the opcode that defines the

sequence to be performed.

The 25CSM04 utilizes an 8-bit instruction register. The

list of instructions and their operation opcodes are

contained in Table 4-1. All instructions, addresses and

data are transferred with the MSb first and are initiated

with a high-to-low CS transition.

TABLE 4-1:

INSTRUCTION SET FOR 25CSM04

Instruction

Instruction Description

Opcode

Address

Bytes

Data

Bytes

Reference

Section

STATUS Register Instructions

RDSR

Read STATUS Register

05h

0000 0101

01 or 2

6.2

WRBP

Write Ready/Busy Poll

08h

0000 1000

6.1.4.1

WREN

Set Write Enable Latch (WEL)

06h

0000 0110

5.1

WRDI

Reset Write Enable Latch (WEL)

04h

0000 0100

5.2

WRSR

Write STATUS Register

01h

0000 0001

01 or 2

6.3

EEPROM and Security Register Instructions

READ

Read from EEPROM Array

03h

0000 0011

31+

7.1

WRITE

Write to EEPROM Array (1 to 256 bytes)

02h

0000 0010

31+

8.0

RDEX

Read from the Security Register

83h

1000 0011

31+

9.1

WREX

Write to the Security Register

82h

1000 0010

31+

9.2

LOCK

Lock the Security Register (permanent)

82h

1000 0010

9.2.1

CHLK

Check Lock Status of Security Register

83h

1000 0011

9.2.2

Memory Partition Register Instructions

RMPR

Read Contents of Memory Partition Registers

31h

0011 0001

10.3

PRWE

Set Memory Partition Write Enable Latch

07h

0000 0111

10.2.1

PRWD

Reset Memory Partition Write Enable Latch

0Ah

0000 1010

10.2.2

WMPR

Write Memory Partition Registers

32h

0011 0010

10.2.3

PPAB

Protect Partition Address Boundaries

34h

0011 0100

10.1.3

FRZR

Freeze Memory Protection Configuration (per-

manent)

37h

0011 0111

4.5.4

Identification Register Instructions

SPID

Read the SPI Manufacturer ID Data

9Fh

1001 1111

11.1

Device Reset Instruction

SRST

Software Device Reset

7Ch

0111 1100

1.1.2

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