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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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25CSM04 датащи(PDF) 35 Page - Microchip Technology |
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25CSM04 датащи(HTML) 35 Page - Microchip Technology |
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35 / 55 page  2019-2022 Microchip Technology Inc. and its subsidiares DS20005817D-page 35 25CSM04 10.1.3 PROTECTING THE PARTITION ENDPOINT ADDRESSES The 25CSM04 includes the ability to protect the Partition Endpoint Addresses specified in the device’s eight MPRs from being modified. When the protection is enabled, the Partition Behavior bits of the MPR can still be modified. As shown in Table 10-2, this function becomes redundant if the FMPC bit in the STATUS register (bit 5, byte 1) is a logic ‘1’ as the result of a FRZR sequence (see Section 4.5.4 “Freeze Memory Protection Configuration (FRZR)”) since the FRZR sequence locks all Partition Endpoint Addresses and Partition Behavior bits. REGISTER 10-1: MEMORY PARTITION REGISTERS R/W R/W R/W R/W R/W R/W R/W R/W PB1 PB0 A18 A17 A16 A15 A14 A13 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PB[1:0]: Partition Behavior bits(1) 00 = Partition is open and writing is permitted. 01 = Partition is always write-protected but can be reversed at a later time (software write-protected). 10 = Partition is write-protected only when WP pin is asserted (hardware write-protected). 11 = Partition is software write-protected and Memory Partition register is permanently locked. bit 5-0 A[18:13]: Partition Endpoint Address bits(1, 2) 000000 = Endpoint address of partition is set to 01FFFh. 000001 = Endpoint address of partition is set to 03FFFh. • • • 111110 = Endpoint address of partition is set to 7DFFFh. 111111 = Endpoint address of partition is set to 7FFFFh. Note 1: The Memory Partition registers cannot be written if the FMPC bit has been set. 2: The Partition Endpoint Address bits cannot be written if the PABP bit has been set. TABLE 10-1: EXAMPLE USE OF MEMORY PARTITION REGISTERS Register Content Partition Behavior Bits (Bit 7-6) Partition Protection Register Protection Partition Ending Address Bits (Bit 5-0) Partition Ending Memory Address Partition Size and Address Range MPR0 43h 01b Software Protection Unlocked 000011b 07FFFh 256-Kbit partition 000000h-007FFFh MPR1 C4h 11b Software Protection Locked 000100b 09FFFh 64-Kbit partition 008000h-009FFFh MPR2(1) 03h 00b Unprotected Unlocked 000011b 07FFFh Register ignored MPR3 8Fh 10b Hardware Protection Unlocked 001111b 01FFFFh 704-Kbit partition 00A000h-01FFFFh Note 1: In this example, MPR2 is ignored because its Partition Endpoint Address was not greater than the ending address specified by MPR1. Note: The PPAB instruction will be ignored if the WPEN bit (byte 0, bit 7) of the STATUS register is set to a logic ‘1’ and the WP pin is asserted. |
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