25CSM04 datasheet(34/55 Pages) MICROCHIP

34 / 55 page

25CSM04

DS20005817D-page 34

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FIGURE 10-1:

25CSM04 MEMORY PARTITION MAP

10.1.2

MEMORY PARTITION REGISTER

ORGANIZATION

Each MPR is an 8-bit nonvolatile register. The MPR

organization is shown in Register 10-1. The four types

of protection behavior are defined by the contents of bit

7 and bit 6 of each MPR (see Register 10-1). Each par-

tition can have a unique behavior.

Bit 5 though bit 0 contain the Partition Endpoint

Address of A18:A13, where A12:A0 are a logic ‘1’. For

example, if the first partition of the memory array is

desired to stop after 128-Kbit of memory, that endpoint

address is 03FFFh. The corresponding A18:A13

address bits to be loaded into MPR0 are therefore

000001b.

The eight MPRs are each decoded sequentially by the

device, starting with MPR0. Each MPR should be set to

a Partition Endpoint Address greater than the ending

address of the previous MPR. If a higher order MPR

sets a Partition Endpoint Address less than or equal to

the ending address of a lower order MPR, that higher

order MPR is ignored and no protection is set by its

contents.

An example use case is provided in Table 10-1.

00000h

01FFFh

02000h

04000h

06000h

03FFFh

05FFFh

07FFFh

7C000h

7E000h

7DFFFh

7FFFFh

32 Pages

Beginning

Address

Ending

Address

64-Kbit

Available Partition Point:

A18:A13 [000000b]

Available Partition Point:

A18:A13 [000001b]

Available Partition Point:

A18:A13 [000010b]

Available Partition Point:

A18:A13 [000011b]

Available Partition Point:

A18:A13 [111110b]

Available Partition Point:

A18:A13 [111111b]

4-Mbit (512-Kbyte) EEPROM

(256 bytes per page x 2,048 pages)

Note:

When the Partition Behavior bits are

written to 11b, that MPR will become

permanently read-only (ROM) and its

contents

cannot

changed

(see

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