25CSM04 datasheet(27/55 Pages) MICROCHIP

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DS20005817D-page 27

25CSM04

8.0

WRITE SEQUENCES

In order to program the EEPROM in the 25CSM04, the

device must be write-enabled via the Write Enable

instruction (WREN). If the device is not write-enabled,

the device will ignore the WRITE instruction and will

return to the Standby state when CS is brought high.

The address of the memory location(s) to be

programmed must be outside the protected address

range(s) selected by the Block Write Protection level or

the contents of the various Memory Partition registers.

During an internal write cycle, all instructions will be

ignored except the RDSR and the WRBP instructions.

8.1

Write Instruction Sequences

8.1.1

BYTE WRITE

Once a WREN instruction has been completed, a byte

write sequence can be performed as shown in

Figure 8-1. After the CS line is pulled low to select the

device, the WRITE (02h) instruction is transmitted via

the SI line followed by the 24-bit address and the data

(D7-D0) to be programmed.

Address bits A23 through A19 are “don’t care” bits

because they do not fall within the addressable

memory range.

Programming will start after the CS pin is brought high.

The low-to-high transition of the CS pin must occur

during the SCK low time (mode 0) and SCK high time

(mode 3) immediately after clocking in the D0 (LSB)

data bit.

The 25CSM04 is automatically returned to the Write

Disable state (STATUS register bit WEL = 0) at the

completion of a write cycle.

FIGURE 8-1:

BYTE WRITE SEQUENCE

8.1.2

PAGE WRITE

A page write sequence is the same as a byte write,

however allowing up to 256 bytes to be written in the

same write cycle, provided that all bytes are in the

same page of the memory array (where addresses A18

through A8 are the same). Partial page writes of less

than 256 bytes are allowed. After each byte of data is

received, the eight lowest order address bits are

internally incremented by one and the remaining

address bits will remain constant.

If more bytes of data are transmitted than what will fit to

the end of that memory page, the address counter will

“rollover” to the beginning of the same page and only

the last 256 bytes of data received will be written to the

device.

Upon completion of a write cycle, the 25CSM04

automatically returns to the Write Disable state

(STATUS register bit WEL = 0).

Note:

If the CS pin is deasserted at somewhere

other than the end of an 8-bit byte

boundary, the sequence will be aborted

and no write cycle will take place.

SCK

234

56 7

9 10 11 12

High-Impedance

00 0 0 0 0

1 0

WRITE Opcode (02h)

Address Bits A23-A0

X XXX X A

D7 D6 D5 D4 D3 D2 D1 D0

Data In

MSb

AA A

833

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

TWC(1)

Note:

If the CS pin is deasserted at somewhere

other than the end of an 8-bit byte

boundary, the sequence will be aborted

and no write cycle will take place.

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