25CSM04 datasheet(28/55 Pages) MICROCHIP

28 / 55 page

25CSM04

DS20005817D-page 28

 2019-2022 Microchip Technology Inc. and its subsidiares

FIGURE 8-2:

PAGE WRITE SEQUENCE

8.2

Error Correction Code (ECC)

Architecture

The 25CSM04 incorporates a built-in Error Correction

Code (ECC) logic scheme. The EEPROM array is

internally organized as a group of four connected bytes

plus an additional six ECC parity bits of EEPROM.

These 38 bits are referred to as the internal physical

data word. During a read sequence, the ECC logic

compares each 4-byte physical data word with its

corresponding six ECC parity bits. If a single bit out of

the 4-byte region happens to read incorrectly, the ECC

logic will detect the bad bit and replace it with a correct

value before the data is serially clocked out. This

architecture significantly improves the reliability of the

25CSM04 versus a device that does not utilize ECC.

It is important to note that data is always physically

written to the part at the internal physical data word

level, regardless of the number of bytes written. Writing

single bytes is still possible with the byte write

sequence, but internally, the other three bytes within

the 4-byte location where the single byte was written,

along with the six ECC parity bits will be updated. Due

to this architecture, the 25CSM04 EEPROM write

endurance is rated at the internal physical data word

level (4-byte word). The system designer needs to

optimize the application writing algorithms to observe

these internal word boundaries in order to maximize

the endurance.

8.3

Polling Routine

A polling routine can be implemented to optimize time

sensitive applications that would not prefer to wait the

fixed maximum write cycle time (TWC). This method

allows the application to query whether the Serial

EEPROM has completed the write sequence. This

polling routine should be initiated once the internally

timed write sequence has begun.

The polling routine is repeatedly sending Read

STATUS Register (RDSR) or Write Ready/Busy Poll

(WRBP) instructions to determine if the device has

completed its self-timed internal write cycle (see

Figure 8-3). If the RDY/BSY bit = 1 from RDSR or FFh

from WRBP the write cycle is still in progress.

If RDY/BSY bit = 0 from RDSR or 00h from WRBP this

indicates the write cycle has ended. If the device is still

in a busy state, repeated RDSR or WRBP instructions

can be executed until the RDY/BSY bit = 0 or the WRBP

instruction returns a 00h, signaling that the device is

ready to execute a new instruction. Only the RDSR and

WRBP instructions are enabled during the write cycle.

FIGURE 8-3:

POLLING FLOW

SCK

234

567

Data In Byte n (256 max.)

MSb

0 0000 0 1 0 X X X

AA A

WRITE Opcode (02h)

Address Bits A23-A0

Data In Byte 1

MSb

D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

833

TWC(1)

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

YES

Send Valid Write

Instruction

Deassert CS High to

Initiate a Write Cycle

Send RDSR/WRBP

Instruction to the Device

Next Sequence

Is WRBP = 00h or is

RDY/BSY = 0?

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