25CSM04 datasheet(30/55 Pages) MICROCHIP

30 / 55 page

25CSM04

DS20005817D-page 30

 2019-2022 Microchip Technology Inc. and its subsidiares

9.1.1

READING THE

FACTORY-PROGRAMMED 128-BIT

SERIAL NUMBER

The Security register contains a factory-programmed,

globally unique, read-only 128-bit serial number. This

serial number is unique across all varieties of Microchip

CS series EEPROM and it is located in the lower 16

bytes of the Security register (bytes 0h-Fh). Reading

the serial number is accomplished in the same way as

the reading of any other data in the Security register.

9.2

Writing to the Security Register

Executing a write sequence to the Security register is

identical to the EEPROM as described in Section 8.1.1

“Byte Write” and Section 8.1.2 “Page Write” with the

exception that the WREX (82h) instruction is used and

A10 must be a logic ‘0’ and A8 must be a logic ‘1’ in

order to write the user-programmable lockable ID page.

In Legacy Write Protection mode, the Security register

is write-protected when the BP [1:0] bits (byte 0, bits

3-2) of the STATUS register = 11. There is no

dependency on the WPEN bit (byte 0, bit 7) of the

STATUS register or the WP pin.

The user-programmable lockable ID page of the

Security register can also be permanently locked such

that its contents also become read-only. This is

accomplished with LOCK instruction. Determining if the

device has previously been locked can be determined

with the CHLK instruction. If the Security register is

locked, any subsequent WREX instructions will be

ignored.

9.2.1

LOCKING THE SECURITY

The upper 256 bytes of the Security register are

shipped by Microchip in a user-programmable state.

Once

the

desired

data

written,

the

user-programmable lockable ID page of the Security

LOCK instruction.

The LOCK instruction is irreversible and will

permanently prevent all future write sequences to the

upper 256 bytes of the Security register on the

25CSM04, thereby rendering the entire 512-byte

Security register read-only.

The LOCK instruction emulates a write sequence in that

a WREN instruction must first be sent to set the WEL bit

in the STATUS register to logic ‘1’. As shown in

Figure 9-4, the LOCK (82h) instruction is clocked in on

the SI line, followed by a dummy address where bits

A23 through A0 are “don’t care” bits with the exception

that bit A10 must be set to ‘1’. Finally, a confirmation

data byte of xxxxxx1xb is sent and the self-timed

internal write cycle will begin once the CS pin is driven

high.

Note:

To ensure a unique number, the 128-bit

serial number must be read from the

starting address. Additionally, the entire

serial number must be read to realize a

completely unique value.

Note:

If the CS pin is deasserted at somewhere

other than the end of an 8-bit byte

boundary, the sequence will be aborted

and no write cycle will take place.

Note:

The LOCK instruction will be ignored if the

WPEN bit (byte 0, bit 7) of the STATUS

is asserted.

Note:

Once the Security register has been

locked, it is not possible to unlock it.

Note:

If the CS pin is deasserted before the end

of the 40-bit sequence, the sequence will

be aborted and no write cycle will take

place.

25CSM04 датащи(PDF) 30 Page - Microchip Technology

25CSM04 датащи(HTML) 30 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

датащи скачать

ссылки URL