ATAR080 datasheet(50/68 Pages) ATMEL

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ATAR080

4675D–4BMCU–12/04

Serial Interface Status and

Control Register (SISC)

Serial Transmit Buffer (STB) –

Byte Write

The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the

shift register and starts shifting with the most significant bit.

Serial Receive Buffer (SRB) –

Byte Read

The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most

significant bit first) and loads the content into the receive buffer when a complete tele-

gram has been received.

Primary register address: ’A’hex

Bit 3Bit 2Bit 1Bit 0

SISC

write

RACK

SIM

IFN

Reset value: 1111b

SISC

read

–

TACK

ACT

SRDY

Reset value: xxxxb

RACK

Receive ACKnowledge status/control bit for MCL mode

RACK = 0, transmit acknowledge in next receive telegram

RACK = 1, transmit no acknowledge in last receive telegram

TACK

Transmit ACKnowledge status/control bit for MCL mode

TACK = 0, acknowledge received in last transmit telegram

TACK = 1, no acknowledge received in last transmit telegram

SIM

Serial Interrupt Mask

SIM = 1, disable interrupts

SIM = 0, enable serial interrupt. An interrupt is generated.

IFN

Interrupt FuNction

IFN = 1, the serial interrupt is generated at the end of the telegram

IFN = 0, the serial interrupt is generated when the SRDY goes low

(i.e., buffer becomes empty/full in transmit/receive mode)

SRDY

Serial interface buffer ReaDY status flag

SRDY = 1, in receive mode: receive buffer empty

in transmit mode: transmit buffer full

SRDY = 0, in receive mode: receive buffer full

in transmit mode: transmit buffer empty

ACT

Transmission ACTive status flag

ACT = 1, transmission is active, i.e., serial data transfer. Stop or start

conditions are currently in progress.

ACT = 0, transmission is inactive

Primary register address: ’9’hex

STB

First write cycle

Bit 3

Bit 2

Bit 1

Bit 0

Reset value: xxxxb

Second write cycle

Bit 7

Bit 6

Bit 5

Bit 4

Reset value: xxxxb

Primary register address: ’9’hex

SRB

First read cycle

Bit 7

Bit 6

Bit 5

Bit 4

Reset value: xxxxb

Second read cycle

Bit 3

Bit 2

Bit 1

Bit 0

Reset value: xxxxb

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