ATAR080 datasheet(20/68 Pages) ATMEL

20 / 68 page

ATAR080

4675D–4BMCU–12/04

Peripheral Modules

Addressing Peripherals

Accessing the peripheral modules takes place via the I/O bus (see Figure 21). The IN or

OUT instructions allow direct addressing of up to 16 I/O modules. A dual register

addressing scheme has been adopted to enable direct addressing of the primary regis-

ter. To address the auxiliary register, the access must be switched with an auxiliary

switching module. Thus, a single IN (or OUT) to the module address will read (or write

into) the modules primary register. Accessing the auxiliary register is performed with the

same instruction preceded by writing the module address into the auxiliary switching

module. Byte wide registers are accessed by multiple IN (or OUT) instructions. For more

complex peripheral modules, with a larger number of registers, extended addressing is

used. In this case, a bank of up to 16 subport registers are indirectly addressed with the

subport address. The first OUT instruction writes the subport address to the

sub-address register, the second IN or OUT instruction reads data from or writes data to

the addressed subport.

Figure 21. Example of I/O Addressing

Subaddress Reg.

Subport FH

I/O bus

Aux. Reg.

Bank of

Primary Regs.

Primary Reg.

(Address Pointer)

Auxiliary Switch

Module

Indirect Subport Access

to other modules

(Subport Register Write)

Example of

qFORTH

Program

Code

Addr. (ASW) = Auxililiary Switch Module Address

(Auxiliary Register Write)

Module ASW

Module M1

Module M2

Module M3

Subport EH

Primary Reg.

Subport 1

Subport 0

Dual Register Access

Single Register Access

Addr. (SPort) Addr. (M1) OUT

SPort_Data

Addr. (M1)

OUT

(Subport Register Read)

Addr. (SPort) Addr. (M1) OUT

Addr. (M1) IN

(Subport Register Write Byte)

Addr. (SPort) Addr. (M1) OUT

SPort_Data (lo) Addr. (M1)

OUT

SPort_Data (hi) Addr. (M1)

OUT

(Subport Register Read Byte)

Addr. (SPort) Addr. (M1) OUT

Addr. (M1) IN (hi)

Addr. (M1) IN (lo)

(Primary Register Write)

Prim._Data Addr. (M2) OUT

Addr. (M2) Addr. (ASW) OUT

Aux._Data Addr. (M2) OUT

(Primary Register Read)

Addr. (M2) IN

(Auxiliary Register Read )

Addr. (M2) Addr. (ASW) OUT

Addr. (M2) IN

(Auxiliary Register Write Byte)

Addr. (M2) Addr. (ASW) OUT

Aux._Data (lo) Addr. (M2)

OUT

Aux._Data (hi) Addr. (M2)

OUT

(Primary Register Write)

Prim._Data Addr. (M3) OUT

(Primary Register Read)

Addr. (M3) IN

Addr. (Mx) = Module Mx Address

Addr. (SPort) = Subport Address

Prim._Data = Data to be written into Primary Register

Aux._Data = Data to be written into Auxiliary Register

Aux._Data (lo) = Data to be written into Auxiliary Register (low nibble)

Aux._Data (hi) = Data to be written into Auxiliary Register (high nibble)

SPort_Data (lo) = Data to be written into Subport (low nibble)

SPort_Data (hi) = Data to be written into Subport (high nibble)

(lo) = SPort_Data (low nibble)

(hi) = SPort_Data (high nibble)

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