ATAR080 datasheet(26/68 Pages) ATMEL

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ATAR080

4675D–4BMCU–12/04

Figure 25. Bi-directional Port 4

Port 4 Data Register (P4DAT)

Port 4 Control Register (P4CR)

Byte Write

P4xM2, P4xM1 – Port 4x Interrupt Mode/Direction Code

Master reset

BPxy

(1) Mask options

(1)

PxDATy

I/O Bus

Pull-up

Pull-down

PxCRy

PxMRy

POut

(Direction)

PDir

Intx

Static pull-up

Static pull-down

(1)

Primary register address: '4'hex

Bit 3

Bit 2

Bit 1

Bit 0

P4DAT

P4DAT3

P4DAT2

P4DAT1

P4DAT0

Reset value: 1111b

Auxiliary register address: '4'hex

Bit 3

Bit 2

Bit 1

Bit 0

P4CR

First write cycle

P41M2

P41M1

P40M2

P40M1

Reset value: 1111b

Bit 7

Bit 6

Bit 5

Bit 4

Second write cycle

P43M2

P43M1

P42M2

P42M1

Reset value: 1111b

Table 12. Port 4 Control Register

Auxiliary Address: '4'hex First Write Cycle

Second Write Cycle

Code

3 2 1 0

Function

Code

3 2 1 0

Function

x x 1 1

BP40 in input mode

x x 1 1

BP42 in input mode

x x 1 0

BP40 in output mode

x x 1 0

BP42 in output mode

x x 0 1

BP40 enable alternate function (SC for SSI)

x x 0 x

BP42 enable alternate function (T2O for Timer 2)

x x 0 0

BP40 enable alternate function (falling edge interrupt

input for INT3)

1 1 x x

BP43 in input mode

1 1 x x

BP41 in input mode

1 0 x x

BP43 in output mode

1 0 x x

BP41 in output mode

0 1 x x

BP43 enable alternate function (SD for SSI)

0 1 x x

BP41 enable alternate function (VMI for voltage

monitor input)

0 0 x x

BP43 enable alternate function (falling edge interrupt

input for INT3)

0 0 x x

BP41 enable alternate function (T2I external clock

input for Timer 2)

––

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