ADUC7023BCBZ62I-R7 datasheet(17/98 Pages) AD

17 / 98 page

Data Sheet

ADuC7023

Rev. H | Page 17 of 98

Pin No.

40-

LFCSP

32-

LFCSP

36-

WLCSP

Mnemonic

Description

P0.3/PLAO[9]/TCK

The default value of this pin depends on the level of P0.0/BM. If P0.0/BM =

0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin

defaults to a JTAG test data clock pin. This is a multifunction pin as follows:

General-Purpose Input and Output Port 0.3.

Programmable Logic Array Output Element 9.

Test Clock, JTAG Test Port Clock Input. Debug and download access. When

debugging the part via JTAG, this pin must not be toggled by user code

and the GP0CON/GP0DAT register bits affecting this pin must not be

changed as doing so disables JTAG access.

DGND

Digital Ground.

IOVDD

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

LVDD

2.6 V Output of the On-Chip Voltage Regulator. This output must be

connected to a 0.47 μF capacitor to DGND only.

RST

Reset Input, Active Low.

RTCK

Return JTAG Clock Signal. This is not the standard JTAG clock signal. It is

an output signal from the JTAG controller. If using a 20-lead JTAG header,

connect to Pin 11.

P0.4/IRQ0/SCL0/PLAI[0]/CONV

General-Purpose Input and Output Port 0.4/External Interrupt Request 0/ I2C0

Clock Signal/Programmable Logic Array Input Element 0/ADC External

Convert Start. By default, this pin is configured as a digital input with a

weak pull-up resistor enabled.

P0.5/SDA0/PLAI[1]/COMPOUT

General-Purpose Input and Output Port 0.5/I2C0 Data Signal/ Programmable

Logic Array Input Element 1/Voltage Comparator Output. By default, this

pin is configured as a digital input with a weak pull-up resistor enabled.

P0.6/MISO/SCL1/PLAI[2]

General-Purpose Input and Output Port 0.6/SPI MISO Signal/I2C1 Clock On

32-Lead and 36-Ball Packages/Programmable Logic Array Input Element 2.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled.

P0.7/MOSI/SDA1/PLAO[0]

General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I2C1 Data

Signal On 32-Lead and 36-Ball Packages/Programmable Logic Array Output

Element 0.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled.

P0.6/MISO/PLAI[2]

General-Purpose Input and Output Port 0.6/SPI MISO Signal/Programmable

Logic Array Input Element 2. By default, this pin is configured as a digital input

with a weak pull-up resistor enabled.

P0.7/MOSI/PLAO[0]

General-Purpose Input and Output Port 0.7/SPI MOSI Signal/Programmable

Logic Array Output Element 0. By default this pin is configured as a digital

input with a weak pull-up reisistor enabled.

XCLKI

Input to the Crystal Oscillator Inverter and Input to the Internal Clock

Generator Circuits. Connect to DGND if unused.

XCLKO

Output from the Crystal Oscillator Inverter. Leave unconnected if unused.

N/A

P1.7/PWM3/SDA1/PLAI[6]

General-Purpose Input and Output Port 1.7/PWM Output 3/I2C1 Data

Signal/Programmable Logic Array Input Element 6. By default, this pin is

configured as a digital input with a weak pull-up resistor enabled.

N/A

P1.6/PWM2/SCL1/PLAI[5]

General-Purpose Input and Output Port 1.6/PWM Output 2/I2C1 Clock

Signal/Programmable Logic Array Input Element 5. By default, this pin is

configured as a digital input with a weak pull-up resistor enabled.

N/A

P1.5/ADC6/PWMTRIPINPUT/PLAO[4]

General-Purpose Input and Output Port 1.5/ADC Single-Ended or

Differential Analog Input 6/PWMTRIPINPUT/Programmable Logic Array

Output Element 4. By default, this pin is configured as a digital input with

a weak pull-up resistor enabled. When used as ADC input, the pull-up

resistor should be disabled manually.

N/A

P1.4/ADC10/PLAO[3]

General-Purpose Input and Output Port 1.4/ADC Single-Ended or Dif-

ferential Analog Input 10/Programmable Logic Array Output Element 3.

By default, this pin is configured as a digital input with a weak pull-up

resistor enabled. When used as ADC input, the pull-up resistor should be

disabled manually.

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