ADUC7023BCBZ62I-R7 datasheet(88/98 Pages) AD

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ADuC7023

Data Sheet

Rev. H | Page 88 of 98

Timer2 (Watchdog Time)

Timer2 has two modes of operation: normal mode and watchdog

mode. The watchdog timer is used to recover from an illegal

software state. When enabled, it requires periodic servicing to

prevent it from forcing a processor reset.

Normal Mode

Timer2 in normal mode is identical to Timer0, except for the

clock source and the count-up functionality. The clock source

is 32 kHz from the PLL and can be scaled by a factor of 1, 16, or

256 (see Figure 44).

32.768kHz

PRESCALER

1, 4, 16, OR 256

16-BIT

UP/DOWN

COUNTER

16-BIT

LOAD

TIMER2

VALUE

TIMER2 IRQ

WATCHDOG RESET

Figure 44. Timer2 Block Diagram

Watchdog Mode

Watchdog mode is entered by setting Bit 5 in the T2CON MMR.

Timer2 decreases from the value present in the T2LD register

until 0. T2LD is used as the timeout. The maximum timeout

can be 512 sec using the prescaler/256, and full-scale in T2LD.

Timer3 is clocked by the internal 32 kHz crystal when operating

in the watchdog mode. To enter watchdog mode successfully,

Bit 5 in the T2CON MMR must be set after writing to the T2LD

MMR.

If the timer reaches 0, a reset or an interrupt occurs, depending

on Bit 1 in the T2CON register. To avoid reset or interrupt, any

value must be written to T2CLRI before the expiration period. This

reloads the counter with T2LD and begins a new timeout period.

When watchdog mode is entered, T2LD and T2CON are write-

protected. These two registers cannot be modified until a reset

clears the watchdog enable bit, which causes Timer2 to exit

watchdog mode.

The Timer2 interface consists of four MMRs: T2LD, T2VAL,

T2CON, and T2CLRI.

T2LD Register

Name:

T2LD

Address:

0xFFFF0360

Default

value:

0x0000

Access:

Read/write

T2LD is a 16-bit register load register that holds the 16-bit

value that is loaded into the counter.

T2VAL Register

Name:

T2VAL

Address:

0xFFFF0364

Default

value:

0xFFFF

Access:

Read

T2VAL is a 16-bit read-only register that represents the current

state of the counter.

T2CON Register

Name:

T2CON

Address:

0xFFFF0368

Default

value:

0x0000

Access:

Read/write

T2CON is the configuration MMR described in Table 104.

Table 104. T2CON MMR Bit Descriptions

Bit

Value

Description

15 to 9

Reserved.

Count up.

This bit is set by the user for Timer2 to count up.

This bit is cleared by the user for Timer2 to

count down by default.

Timer2 enable bit.

This bit is set by the user to enable Timer2. This

bit is cleared by user to disable Timer2 by

default.

Timer2 mode.

This bit is set by user to operate in periodic

mode.

This bit is cleared by the user to operate in free-

running mode. Default mode.

Watchdog mode enable bit.

This bit is set by the user to enable watchdog

mode.

This bit is cleared by the user to disable

watchdog mode by default.

Secure clear bit.

This bit is set by the user to use the secure clear

option.

This bit is cleared by the user to disable the

secure clear option by default.

3 to 2

Prescale.

Source clock/1 by default.

Source clock/16.

Source clock/256.

Undefined. Equivalent to 00.

Watchdog IRQ Option Bit.

This bit is set by the user to produce an IRQ

instead of a reset when the watchdog reaches 0.

This bit is cleared by the user to disable the IRQ

option.

Reserved.

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