ADUC7023BCBZ62I-R7 datasheet(89/98 Pages) AD

89 / 98 page

Data Sheet

ADuC7023

Rev. H | Page 89 of 98

T2CLRI Register

Name:

T2CLRI

Address:

0xFFFF036C

Default value:

0xXX

Access:

Write

T2CLRI is an 8-bit register. Writing any value to this register

on successive occassions clears the Timer2 interrupt in normal

mode or resets a new timeout period in watchdog mode.

The user must perform successive writes to this register to ensure

resetting the timeout period.

Secure Clear Bit (Watchdog Mode Only)

The secure clear bit is provided for a higher level of protection.

When set, a specific sequential value must be written to

T2CLRI to avoid a watchdog reset. The value is a sequence

generated by the 8-bit linear feedback shift register (LFSR)

polynomial = X8 + X6 + X5 + X + 1 shown in Figure 45.

The initial value or seed is written to T2CLRI before entering

watchdog mode. After entering watchdog mode, a write to T2CLRI

must match this expected value. If it matches, the LFSR is advanced

to the next state when the counter reload happens. If it fails to

match the expected state, a reset is immediately generated, even

if the count has not yet expired.

The value 0x00 should not be used as an initial seed due to the

properties of the polynomial. The value 0x00 is always guaranteed

to force an immediate reset. The value of the LFSR cannot be read;

it must be tracked/generated in software.

An example of a sequence follows:

Enter initial seed, 0xAA, in T2CLRI before starting Timer2

in watchdog mode.

Enter 0xAA in T2CLRI; Timer2 is reloaded.

Enter 0x37 in T2CLRI; Timer2 is reloaded.

Enter 0x6E in T2CLRI; Timer2 is reloaded.

Enter 0x66. 0xDC was expected; the watchdog resets the chip.

CLOCK

Figure 45. 8-Bit LFSR

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